Semiconductor device with reduced leakage current and method for manufacture the same

Abstract

A semiconductor device with reduced leakage current and a method of manufacturing these reduced leakage current semiconductor devices are disclosed. The reduced leakage current semiconductor devices may be used for both static circuits and dynamic circuits. The reduced leakage current semiconductor devices reduce leakage current in the device when the node is not transitioning which occurs more than 95% of the time.

1 . A low leakage current CMOS device that has one or more power rails, the device comprising:
 an input, an output and a logic function circuit that receives an input signal on the input and generates an output signal on the output;   a voltage translator that drives a voltage swing differential on the input and output or one of the input and output;   a current control decision circuit that monitors and generates signals to control flow of transition and leakage current and   a current control circuit that has a deterministic voltage offset to the input voltage swing so that the device has reduced leakage current and controls timing, magnitude and location of currents including transition current and leakage current.   
     
     
         2 . The device of  claim 1 , wherein the current control circuit further comprises a pull up current control circuit and a pull down current control circuit. 
     
     
         3 . The device of  claim 1 , wherein the logic function circuit further comprises a pull-up logic circuit coupled to the pull up current control circuit and a pull-down logic circuit coupled to the pull down current control circuit. 
     
     
         4 . The device of  claim 1  further comprising a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first voltage supply delivers a larger voltage than the second voltage supply and the third voltage supply delivers a larger voltage than the fourth voltage supply and first and second voltage supply deliver voltage larger than third and fourth voltage supply. 
     
     
         5 . The device of  claim 1  further comprising a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first and fourth voltage supplies are connected to the voltage translator and the second and third voltage supplies are connected to the current control circuit. 
     
     
         6 . The device of  claim 5 , wherein the first voltage supply further comprises a Vdd voltage added to a delta voltage and the fourth voltage supply further comprises a second delta voltage subtracted from a Vss voltage. 
     
     
         7 . The device of  claim 1 , wherein the logic function circuit is an inverter. 
     
     
         8 . The device of  claim 1 , wherein the logic function circuit is a NAND2 logic gate. 
     
     
         9 . A low leakage current CMOS device that has at least three power rails, the device comprising:
 an input, an output and a logic function circuit that receives an input signal on the input and generates an output signal on the output;   a voltage translator having a PMOS transistor and an NMOS transistor coupled to a first power rail and a second power rail, the voltage translator driving a voltage swing differential on the input and output;   a current control decision circuit that monitors and generates signals to control flow of transition and leakage current; and   a current control circuit having a PMOS transistor and an NMOS transistor coupled to a third power rail and a fourth power rail, the current control circuit having a deterministic voltage offset to the input voltage swing so that the device has reduced leakage current and controls timing, magnitude and location of currents including transition current and leakage current.   
     
     
         10 . The device of  claim 9 , wherein the PMOS transistor and an NMOS transistor of the current control circuit are each high speed transistors. 
     
     
         11 . The device of  claim 10 , wherein the PMOS transistor and an NMOS transistor of the voltage translator are each low leakage transistors. 
     
     
         12 . The device of  claim 11 , wherein the PMOS transistor of the current control circuit is a uni-directional high speed PMOS transistor and the NMOS transistor of the current control circuit is a uni-directional high speed NMOS transistor. 
     
     
         13 . The device of  claim 9 , wherein the current control circuit further comprises a pull up set of PMOS and NMOS transistors and a pull down set of PMOS and NMOS transistors. 
     
     
         14 . The device of  claim 13 , wherein the logic function circuit further comprises a pull-up logic circuit coupled to the pull up current control circuit and a pull-down logic circuit coupled to the pull down current control circuit. 
     
     
         15 . The device of  claim 9 , wherein the first power rail has a Vdd voltage added to a delta voltage and the second power rail has a second delta voltage subtracted from a Vss voltage. 
     
     
         16 . The device of  claim 9 , wherein the logic function circuit is an inverter. 
     
     
         17 . The device of  claim 9 , wherein the logic function circuit is a NAND2 logic gate. 
     
     
         18 . A memory with reduced leakage current CMOS, comprising:
 an array of memory bit cells;   a set of reduced leakage current sense amplifiers using deterministic negative gate-source voltage that sense bits of data on the array of memory bit cells;   a reduced leakage current address decoder using deterministic negative gate-source voltage that decodes an address used to one of read and write data to and from the array of memory bit cells; and   a reduced leakage current controller using deterministic negative gate-source voltage that controls the operation of the set of reduced leakage current sense amplifiers and the reduced leakage current address decoder.   
     
     
         19 . The method of  claim 18 , wherein each of the set of reduced leakage current sense amplifiers and the reduced leakage current address decoder further comprises an input, an output and a logic function circuit that receives an input signal on the input and generates an output signal on the output; a voltage translator that drives a voltage swing differential on the input and output; a current control decision circuit that controls a voltage swing based on a negative gate-source voltage applied to the voltage translator; and a current control circuit that has a deterministic voltage offset to the input voltage swing so that the device has reduced leakage current due to negative gate source voltage. 
     
     
         20 . The memory of  claim 18 , wherein the reduced leakage current address decoder comprises of reduced leakage current word line driver. 
     
     
         21 . The reduced leakage current address decoder of driver of  claim 18  where the word line driver further comprises an input, an output and a logic function circuit that receives an input signal on the input and generates an output signal on the output; a voltage translator that drives a voltage swing differential on the input and output; a current control decision circuit that controls a voltage swing based on a negative gate-source voltage applied to the voltage translator; and a current control circuit that has a deterministic voltage offset to the input voltage swing so that the device has reduced leakage current due to negative gate source voltage. 
     
     
         22 . The memory of  claim 18 , wherein each memory bit cell has a reduced leakage current pass transistor because of negative gate-source voltage applied by the word line driver. 
     
     
         23 . The memory of  claim 19 , wherein the current control circuit further comprises a pull up current control circuit and a pull down current control circuit. 
     
     
         24 . The memory of  claim 23 , wherein the logic function circuit further comprises a pull-up logic circuit coupled to the pull up current control circuit and a pull-down logic circuit coupled to the pull down current control circuit. 
     
     
         25 . The memory of  claim 19  further comprising a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first voltage supply delivers a larger voltage than the second voltage supply and the third voltage supply delivers a larger voltage than the fourth voltage supply and supply 1  and supply  2  are larger than supply  3  and supply 4 . 
     
     
         26 . The memory of  claim 19  further comprising a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first and fourth voltage supplies are connected to the voltage translator and the second and third voltage supplies are connected to the current control circuit. 
     
     
         27 . The memory of  claim 26 , wherein the first voltage supply further comprises a Vdd voltage added to a delta voltage and the fourth voltage supply further comprises a second delta voltage subtracted from a Vss voltage. 
     
     
         28 . A reduced leakage current CMOS dynamic circuit, comprising:
 a pull up circuit block with at least one component connected to a pre-charge signal;   a clocked pull down circuit block connected to at least one primary input of the dynamic circuit; and   a reduced leakage current inverter having an input connected to the pull up circuit block and the clocked pull down circuit block and an output connected to an output of the dynamic circuit.   
     
     
         29 . The dynamic circuit of  claim 28 , wherein the reduced leakage current inverter further comprises an input, an output and an inverter logic circuit that receives an input signal on the input and generates an output signal on the output; a voltage translator that drives a voltage swing differential on the input and output; a current control decision circuit that monitors and generates signals to control flow of transition and leakage current; and a current control circuit that has a deterministic voltage offset to the input voltage swing so that the device has reduced leakage current and controls timing, magnitude and location of currents including transition current and leakage current. 
     
     
         30 . The dynamic circuit of  claim 29 , wherein the current control circuit further comprises a pull up current control circuit and a pull down current control circuit. 
     
     
         31 . The dynamic circuit of  claim 30 , wherein the inverter further comprises a pull-up logic circuit coupled to the pull up current control circuit and a pull-down logic circuit coupled to the pull down current control circuit. 
     
     
         32 . The dynamic circuit of  claim 30  further comprising a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first voltage supply delivers a larger voltage than the second voltage supply and the third voltage supply delivers a larger voltage than the fourth voltage supply and first and second voltage supply deliver voltage larger than third and fourth voltage supply. 
     
     
         33 . The dynamic circuit of  claim 30  further comprising a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first and fourth voltage supplies are connected to the voltage translator and the second and third voltage supplies are connected to the current control circuit. 
     
     
         34 . The dynamic circuit of  claim 33 , wherein the first voltage supply further comprises a Vdd voltage added to a delta voltage and the fourth voltage supply further comprises a second delta voltage subtracted from a Vss voltage. 
     
     
         35 . A method for constructing a low leakage current CMOS device that has one or more power rails, an input, an output and a logic function circuit that receives an input signal on the input and generates an output signal on the output, the method comprising:
 driving, by a voltage translator connected to the logic function circuit, a voltage swing differential on one of the input and the output;   controlling, by a current control decision circuit connected to the voltage translator and the logic function circuit, the flow of transition and leakage current; and   generating, by a current control circuit connected to the voltage translator, the current control decision circuit and the logic function circuit, a deterministic voltage offset to the input voltage swing so that the device has reduced leakage current and controlling timing, magnitude and location of currents including transition current and leakage current.   
     
     
         36 . The method of  claim 35 , wherein generating the deterministic voltage offset further comprises generating the deterministic voltage offset by at least one of a pull up current control circuit and a pull down current control circuit. 
     
     
         37 . The method of  claim 36  further comprising providing a logic function circuit wherein the logic function circuit further comprises a pull-up logic circuit coupled to the pull up current control circuit and a pull-down logic circuit coupled to the pull down current control circuit. 
     
     
         38 . The method of  claim 35  further comprising providing a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first voltage supply delivers a larger voltage than the second voltage supply and the third voltage supply delivers a larger voltage than the fourth voltage supply and first and second voltage supply deliver voltage larger than third and fourth voltage supply. 
     
     
         39 . The method of  claim 35  further comprising providing a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first and fourth voltage supplies are connected to the voltage translator and the second and third voltage supplies are connected to the current control circuit. 
     
     
         40 . The method of  claim 37 , wherein providing the logic function circuit further comprises providing an inverter. 
     
     
         41 . The method of  claim 37 , wherein providing the logic function circuit further comprises providing a NAND2 logic gate. 
     
     
         42 . A method for constructing a CMOS based logic function gate, the method comprising:
 providing an input receiver block that receives an input to a logic function block;   connecting a logic function block to the input receiver block, the logic function block performing a logic function of the logic function gate based on the input;   connecting an output driver block to the logic function block, the output driver block driving an output from the logic function block.   
     
     
         43 . The method of  claim 42  further comprising connecting a noise filter block to the input receiver block, the output driver block and the logic function block to filter noise. 
     
     
         44 . The method of  claim 42  further comprising providing a voltage translator that generates a voltage swing differential on the input and the output, providing a current control decision circuit that monitors and generates signals to control flow of transition and leakage current and providing a current control circuit that generates a deterministic voltage offset to the input voltage swing so that the logic function circuit has reduced leakage current and controls timing, magnitude and location of currents including transition current and leakage current. 
     
     
         45 . The method of  claim 44 , wherein providing the current control circuit further comprises providing at least one of a pull up current control circuit and a pull down current control circuit. 
     
     
         46 . The method of  claim 44 , wherein providing a logic function block further comprises providing one of a pull-up logic circuit coupled to the pull up current control circuit and a pull-down logic circuit coupled to the pull down current control circuit. 
     
     
         47 . The method of  claim 44  further comprising providing a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first voltage supply delivers a larger voltage than the second voltage supply and the third voltage supply delivers a larger voltage than the fourth voltage supply and first and second voltage supply deliver voltage larger than third and fourth voltage supply. 
     
     
         48 . The method of  claim 44  further comprising providing a first voltage supply, a second voltage supply, a third voltage supply and a fourth voltage supply wherein the first and fourth voltage supplies are connected to the voltage translator and the second and third voltage supplies are connected to the current control circuit. 
     
     
         49 . A CMOS device, comprising:
 one or more high speed transistors each having a gate connected to an input of the CMOS device and an output connected to an output of the CMOS device, the one or more high speed transistors being connected to a first set of power rails;   one or more low leakage transistors each having a gate connected to the input of the CMOS device and an output connected to the output of the CMOS device, the one or more low leakage transistors being connected to a second set of power rails;   the one or more high speed transistors having a negative gate-source voltage applied to them in a steady state to reduce leakage current and the one or more low leakage transistors hold the stead state.   
     
     
         50 . The CMOS device of  claim 49 , wherein the one or more high speed transistors are a PMOS device and an NMOS device. 
     
     
         51 . The CMOS device of  claim 49 , wherein the one or more low leakage transistors are a PMOS device and an NMOS device.