Integrated circuits with cascode transistor

Abstract

An integrated circuit includes an analog circuit including a first transistor. At least one cascode transistor is electrically coupled with the first transistor in a series fashion. A drain and a gate of the cascode transistor are electrically coupled with a gate of the first transistor of the analog circuit. The at least one cascode transistor is operated in a saturation mode or a sub-threshold mode.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 an analog circuit including a first transistor; and   at least one cascode transistor electrically coupled with the first transistor in a series fashion, wherein a drain and a gate of the cascode transistor are electrically coupled with a gate of the first transistor of the analog circuit, and the at least one cascode transistor is operated in a saturation mode or a sub-threshold mode.   
     
     
         2 . The integrated circuit of  claim 1 , wherein a threshold voltage of the at least one cascode transistor is lower than a threshold voltage of the first transistor. 
     
     
         3 . The integrated circuit of  claim 2 , wherein a channel length of the at least one cascode transistor is shorter than a channel length of the first transistor. 
     
     
         4 . The integrated circuit of  claim 2 , wherein a channel width of the at least one cascode transistor is wider than a channel width of the first transistor. 
     
     
         5 . The integrated circuit of  claim 2 , wherein the at least one cascode transistor includes at least one native transistor and the first transistor is not a native transistor. 
     
     
         6 . The integrated circuit of  claim 2 , wherein a dopant concentration in a channel region of the at least one cascode transistor is lower than that of the first transistor. 
     
     
         7 . The integrated circuit of  claim 1  further comprising:
 a bias circuit electrically coupled with a well region of the at least one cascode transistor, wherein the bias circuit is configured to lower a threshold voltage of the at least one cascode transistor. 
 
     
     
         8 . The integrated circuit of  claim 7 , wherein the at least one cascode transistor includes at least one N-type cascode transistor and the bias circuit comprises:
 a second transistor and a third transistor electrically coupled to each other in a series fashion, wherein a gate and a drain of the third transistor are electrically coupled with a node between the second and third transistors, and the node between the second and third transistors is electrically coupled with the well region of the at least one N-type cascode transistor.   
     
     
         9 . The integrated circuit of  claim 1 , wherein the at least one cascode transistor includes at least one P-type cascode transistor and the bias circuit comprises:
 a second transistor and a third transistor electrically coupled to each other in a series fashion, wherein a gate and a drain of the second transistor are electrically coupled to each other, and a node between the second and third transistors is electrically coupled with a well region of the at least one P-type cascode transistor.   
     
     
         10 . The integrated circuit of  claim 1 , wherein the analog circuit is an operational amplifier, a constant-gm bias circuit, a pump circuit, a converter, a multiplexer, or a bandgap reference circuit. 
     
     
         11 . An integrated circuit comprising:
 an analog circuit including a first transistor; and   at least one cascode transistor electrically coupled with the first transistor in a series fashion, wherein a drain and a gate of the cascode transistor are electrically coupled with a gate of the first transistor of the analog circuit, and the at least one cascode transistor includes at least one of a native transistor, a low threshold voltage (LVT) transistor, and an ultra-low threshold voltage (ULVT) transistor.   
     
     
         12 . The integrated circuit of  claim 11 , wherein the at least one cascode transistor is operated in a saturation mode or a sub-threshold mode. 
     
     
         13 . The integrated circuit of  claim 11  further comprising:
 a bias circuit electrically coupled with a well region of the at least one cascode transistor, wherein the bias circuit is configured to lower a threshold voltage of the at least one cascode transistor. 
 
     
     
         14 . The integrated circuit of  claim 13 , wherein the at least one cascode transistor includes at least one N-type cascode transistor and the bias circuit comprises:
 a second transistor and a third transistor electrically coupled to each other in a series fashion, wherein a gate and a drain of the third transistor are electrically coupled with a node between the second and third transistors, and the node between the second and third transistors is electrically coupled with the well region of the at least one N-type cascode transistor.   
     
     
         15 . The integrated circuit of  claim 13 , wherein the at least one cascode transistor includes at least one P-type cascode transistor and the bias circuit comprises:
 a second transistor and a third transistor electrically coupled to each other in a series fashion, wherein a gate and a drain of the second transistor are electrically coupled to each other, and a node between the second and third transistors is electrically coupled with the well region of the at least one P-type cascode transistor.   
     
     
         16 . The integrated circuit of  claim 11 , wherein the analog circuit is an operational amplifier, a constant-gm bias circuit, a pump circuit, a converter, a multiplexer, or a bandgap reference circuit. 
     
     
         17 . An integrated circuit comprising:
 a first P-type cascode transistor electrically coupled with a first P-type transistor in a series fashion; and   a second P-type cascode transistor electrically coupled with a second P-type transistor in a series fashion, wherein gates of the first P-type cascode transistor, the second P-type cascode transistor, the first P-type transistor, and the second P-type transistor are electrically coupled to each other and with a drain of the first P-type cascode transistor.   
     
     
         18 . The integrated circuit of  claim 17  further comprising:
 a first N-type cascode transistor and a first N-type transistor electrically coupled with the first P-type cascode transistor and the first P-type transistor in a series fashion; 
 a second N-type cascode transistor and a second N-type transistor electrically coupled with the second P-type cascode transistor and the second P-type transistor in a series fashion; and 
 a third P-type cascode transistor, a third P-type transistor, a third N-type cascode transistor, and a third N-type transistor electrically coupled in a series fashion,
 wherein gates of the third P-type cascode transistor and the third P-type transistor are electrically coupled to gates of the first P-type cascode transistor, the second P-type cascode transistor, the first P-type transistor, and the second P-type transistor, and 
 wherein gates of the third N-type cascode transistor and the third N-type transistor are electrically coupled with gates of the first N-type cascode transistor and the second N-type cascode transistor and with a drain of the third N-type cascode transistor. 
 
 
     
     
         19 . The integrated circuit of  claim 17  further comprising:
 a first N-type cascode transistor, a first N-type transistor, and a resistor electrically coupled with the first P-type cascode transistor and the first P-type transistor in a series fashion; and 
 a second N-type cascode transistor and a second N-type transistor electrically coupled with the second P-type cascode transistor and the second P-type transistor in a series fashion,
 wherein gates of the first N-type cascode transistor, the second N-type cascode transistor, the first N-type transistor, and the second N-type transistor are electrically coupled to each other and with a drain of the second N-type transistor. 
 
 
     
     
         20 . The integrated circuit of  claim 17  further comprising:
 a first N-type cascode transistor, a first N-type transistor, a first resistor, a second resistor, and a bipolar transistor electrically coupled with the first P-type cascode transistor and the first P-type transistor in a series fashion; and 
 a second N-type cascode transistor, a second N-type transistor, a third resistor, and a second bipolar transistor electrically coupled with the second P-type cascode transistor and the second P-type transistor in a series fashion,
 wherein gates of the first N-type cascode transistor, the second N-type cascode transistor, the first N-type transistor, and the second N-type transistor are electrically coupled to each other and with a drain of the second N-type transistor.