Semiconductor device

Abstract

The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.

1 - 6 . (canceled) 
     
     
         7 . A semiconductor device comprising:
 a memory array arranged in row and columns and having a plurality of nonvolatile memory cells each provided with at least a charge storage layer for storing data therein and an erase gate for erasing data, said memory array being divided into a plurality of blocks;   an erase control circuit which is provided in common to the blocks and controls the operation of applying an erase voltage to at least the erase gate in response to an erase mode instruction with respect to the selected block of the memory array to thereby erase data stored in each nonvolatile memory cell in the selected block; and   a data access control circuit which is provided in common to the blocks and controls the operation of performing data access to each nonvolatile memory cell of the corresponding block different from the selected block during application of the erase voltage to the selected block in response to an access instruction.   
     
     
         8 . The semiconductor device according to  claim 7 ,
 wherein upon execution of an erase verify operation, the erase control circuit outputs a signal indicative of the erase verify operation to the outside, and   wherein the data access control circuit outputs a signal indicative of internal data access to the outside.   
     
     
         9 . The semiconductor device according to  claim 7 ,
 wherein the erase control circuit includes an erase verify controller which controls the operation of verifying whether the corresponding memory cell of the selected block is in an erase state upon erasure, and   wherein when the erase verify controller is executing erase verify control at an external data access request, the data access control circuit operation-controls the erase verify controller to stop the erase verify operation thereof and thereby execute an access operation corresponding to the data access request, and after the completion of the access operation corresponding to the data access request, the data access control circuit releases the stop of the control operation of the erase verify controller to continue the erase verify operation.   
     
     
         10 . The semiconductor device according to  claim 7 , further including a first-in first-out register which sequentially stores therein erase addresses each used to designate a block for specifying an erase object in the memory array,
 wherein the erase control circuit sequentially executes erase operation control on the blocks each targeted for erasure in accordance with the erase addresses stored in the first-in first-out register.   
     
     
         11 . The semiconductor device according to  claim 7 , further including:
 a plurality of registers each of which stores therein the erase address for designating each block target for erasure in the memory array; and   a timer which counts a time interval for defining an erase period,   wherein the erase control circuit executes an erase operation on the erase-target block in parallel in accordance with each of the erase addresses stored in the registers and defines the longest period for the erase operation, based on a count value of the timer.   
     
     
         12 . The semiconductor device according to  claim 11 , wherein the erase control circuit resets the timer to an initial value upon storage of the erase address to each of the registers and allows the timer to perform a count operation from the initial value. 
     
     
         13 . The semiconductor device according to  claim 7 ,
 wherein the blocks are arranged in such a manner that the two blocks are paired, and   wherein the erase control circuit and the data access control circuit perform control to select a block predetermined so as to be paired with the selected block in parallel in response to an external data write instruction and execute erasure on the selected block and writing to the predetermined block in parallel, and perform alternate switching of the blocks target for writing and erasure at the paired blocks.   
     
     
         14 . The semiconductor device according to  claim 7 , wherein each of the nonvolatile memory cells includes:
 a selection transistor having a single layer selection gate and selectively brought into conduction in response to a selection signal;   a memory transistor of a single layer gate structure, coupled in series to the selection transistor and having a charge storage layer placed in a floating state, which accumulates an electrical charge therein; and   an erase gate which is disposed in a memory boundary region and formed over a device isolation film for separating the adjacent memory cells from each other and which transfers an electrical charge to the charge storage layer upon an erase operation.   
     
     
         15 . The semiconductor device according to  claim 7 ,
 wherein each of the nonvolatile memory cells includes:   a selection transistor which has first and second selection gate layers stacked over each other and short-circuited electrically and which is selectively brought into conduction in response to a selection signal;   a charge storage layer placed in a floating state, which is coupled in series to the selection transistor and accumulates an electrical charge therein;   a memory transistor of a stacked gate structure, which is formed over the charge storage layer and has a control gate for controlling a transfer of an electrical charge to the charge storage layer; and   an erase gate which is disposed in a memory cell boundary region and formed over an insulating film for separating the adjacent memory cells from each other and which transfers an electrical charge to the charge storage layer upon an erase operation.   
     
     
         16 . The semiconductor device according to  claim 7 ,
 wherein each of the nonvolatile memory cells includes:   a charge storage layer placed in a floating state, which is formed over a substrate region and accumulates an electrical charge therein;   a selection gate to which a signal for selecting the non-volatile memory cell is applied upon at least data reading; and   an erase gate which is disposed over the substrate region in parallel with the selection gate and transfers an electrical charge to the charge storage layer upon erasure.   
     
     
         17 . A semiconductor device comprising:
 a memory array arranged in rows and columns and having a plurality of nonvolatile memory cells each storing information therein on a non-volatile basis,   wherein each of the nonvolatile memory cells includes:   a selection transistor which has a single layer selection gate and is selectively brought to conduction in response to a selection signal;   a memory transistor of a single layer gate structure, which is coupled in series to the selection transistor and has a charge storage layer placed in a floating state, which accumulates an electrical charge therein and a first impurity region coupled to a source line; and   an erase gate which is disposed in a surface of an isolation film for separating the adjacent memory cells from each other and transfers an electrical charge to the charge storage layer upon an erase operation, and   wherein said semiconductor device includes: a plurality of word lines disposed corresponding to the respective rows of the memory cells and to which the selection gates of the nonvolatile memory cells in their corresponding rows are coupled; and a plurality of bit lines disposed corresponding to the respective columns of the memory cells and to which second impurity regions of the selection transistors of the memory cells in their corresponding columns are coupled.   
     
     
         18 . A semiconductor device comprising:
 a memory array arranged in rows and columns and having a plurality of nonvolatile memory cells each storing information therein on a non-volatile basis,   wherein each of the nonvolatile memory cells includes:   a selection transistor which has first and second selection gate layers stacked over each other and electrically short-circuited and which is selectively brought into conduction in response to a selection signal;   a memory transistor of a stacked gate structure, which is coupled in series with the selection transistor and has a charge storage layer placed in a floating state, which accumulates an electrical charge therein and a control gate which is formed over the chare storage layer and controls a transfer of an electrical charge to the charge storage layer; and   an erase gate which is formed in a surface of an isolation film for separating the adjacent memory cells from each other and transfers an electrical charge to the charge storage layer upon an erase operation, and   wherein said semiconductor device includes:   a plurality of word lines disposed corresponding to the respective rows of the memory cells and coupled to selection gates of the selection transistors of the memory cells in their corresponding rows are coupled; and   a plurality of bit lines disposed corresponding to the respective columns of the memory cells and coupled to impurity regions of the selection transistors of the memory cells in their corresponding columns.