Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors

Abstract

In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.

1 .- 9 . (canceled) 
     
     
         10 . A method, comprising:
 forming a layer stack above first and second conductive lines formed in a device level of a semiconductor device, said layer stack comprising a first stress-inducing dielectric layer and an etch stop layer formed above said first stress-inducing dielectric layer;   forming a mask so as to expose said second conductive lines and cover said first conductive lines;   performing an etch sequence to remove said first stress-inducing dielectric layer and said etch stop layer from above said second conductive lines and reduce a width of sidewall spacer elements formed on sidewalls of said second conductive lines, wherein reducing said width comprises removing a first thickness portion of said sidewall spacer elements while leaving a second thickness portion of said sidewall spacer elements adjacent to said sidewalls;   after performing said etch sequence, forming a second stress-inducing dielectric layer above said second conductive lines and on a portion of said etch stop layer located above said first conductive lines; and   selectively removing said second stress-inducing dielectric layer from above said first conductive lines by using said etch stop layer as an etch stop.   
     
     
         11 . The method of  claim 10 , wherein performing said etch sequence comprises performing a first etch process to expose at least a portion of said first stress-inducing dielectric layer and performing a second etch process to remove a portion of said first stress-inducing dielectric layer, wherein at least a portion of said etch stop layer remains in a space between at least an adjacent two of said second conductive lines after performing said first etch process. 
     
     
         12 . The method of  claim 10 , further comprising introducing an etch indicator species into a surface of said first stress-inducing dielectric layer prior to forming said etch stop layer and controlling at least one etch process of said sequence on the basis of said etch indicator species. 
     
     
         13 . The method of  claim 10 , further comprising rounding corners of a recess formed in an isolation region between at least an adjacent two of said second conductive lines. 
     
     
         14 . The method of  claim 10 , further comprising introducing an etch indicator material in a surface portion of said device level prior to forming said first stress-inducing dielectric layer. 
     
     
         15 . The method of  claim 10 , further comprising forming a bottom etch stop layer as a first layer of said layer stack prior to forming said first stress-inducing dielectric layer. 
     
     
         16 . The method of  claim 10 , wherein said first stress-inducing dielectric layer is formed with an internal tensile stress level and said second stress-inducing layer is formed with an internal compressive stress level. 
     
     
         17 . The method of  claim 10 , wherein said first stress-inducing dielectric layer is formed with an internal compressive stress level and said second stress-inducing layer is formed with an internal tensile stress level. 
     
     
         18 .- 24 . (canceled) 
     
     
         25 . The method of  claim 11 , wherein performing said second etch process comprises removing at least a first part of said remaining portion of said etch stop layer. 
     
     
         26 . The method of  claim 10 , wherein selectively removing said second stress-inducing dielectric layer from above said first conductive lines comprises forming an etch mask above said second conductive lines. 
     
     
         27 . A method, comprising:
 forming first and second conductive lines in a device level of a semiconductor device, at least a portion of each of said first and second conductive lines extending above an isolation structure of said semiconductor device;   forming a layer stack above said first and second conductive lines, said layer stack comprising a first stress-inducing layer and an etch stop layer formed above said first stress-inducing layer;   forming a patterned etch mask above said semiconductor device, said patterned etch mask exposing said second conductive lines and covering said first conductive lines;   performing an etch sequence to remove said first stress-inducing layer and said etch stop layer from above said second conductive lines and to reduce a width of sidewall spacer elements formed on sidewalls of said second conductive lines, wherein reducing said width comprises removing a first thickness portion of said sidewall spacer elements while leaving a second thickness portion of said sidewall spacer elements adjacent to said sidewalls;   after performing said etch sequence, forming a second stress-inducing layer above said semiconductor device, said second stress-inducing layer covering said first and second conductive lines and having an opposite type of stress from said first stress-inducing layer; and   selectively removing said second stress-inducing layer from above said first conductive lines.   
     
     
         28 . The method of  claim 27 , wherein performing said etch sequence comprises:
 performing a first etch process to expose at least a portion of said first stress-inducing layer;   performing a second etch process to remove a first portion of said first stress-inducing layer; and   performing a third etch process to remove a remaining portion of said first stress-inducing layer.   
     
     
         29 . The method of  claim 28 , wherein at least a portion of said etch stop layer remains in a space between at least an adjacent two of said second conductive lines after performing said first etch process. 
     
     
         30 . The method of  claim 27 , wherein reducing said width of said sidewall spacer elements comprises increasing at least a width of a recess formed in said isolation structure between at least an adjacent two of said second conductive lines. 
     
     
         31 . The method of  claim 30 , further comprising rounding at least inside corners of said recess. 
     
     
         32 . The method of  claim 27 , further comprising forming a bottom etch stop layer above said first and second conductive lines prior to forming said first stress-inducing layer. 
     
     
         33 . The method of  claim 27 , wherein forming said first stress-inducing layer comprises forming a stressed dielectric material layer having an intrinsic tensile stress level of up to approximately 1 GPa. 
     
     
         34 . The method of  claim 27 , wherein forming said first stress-inducing layer comprises forming a stressed dielectric material layer having an intrinsic compressive stress level of up to approximately 2 GPa. 
     
     
         35 . The method of  claim 27 , wherein selectively removing said second stress-inducing layer from above said first conductive lines comprises forming a second patterned etch mask above said semiconductor device and performing an etch process. 
     
     
         36 . The method of  claim 35 , wherein selectively removing said second stress-inducing layer from above said first conductive lines further comprises using said etch stop layer formed above said first conductive lines as an etch stop during said etch process. 
     
     
         37 . The method of  claim 35 , wherein selectively removing said second stress-inducing layer from above said first conductive lines further comprises performing a surface treatment to incorporate an etch indicator species into said first stress-inducing layer and using and endpoint detection technique to detect said etch indicator species during said etch process.