US2013093062A1PendingUtilityA1

Semiconductor structure and process thereof

Assignee: LIN YING-CHIHPriority: Oct 18, 2011Filed: Oct 18, 2011Published: Apr 18, 2013
Est. expiryOct 18, 2031(~5.2 yrs left)· nominal 20-yr term from priority
H10P 50/693H10P 50/28H10D 86/215H10D 86/011H10D 30/6211H10D 30/024
48
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Claims

Abstract

A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

Claims

exact text as granted — not AI-modified
1 . A semiconductor structure, comprising:
 a substrate;   a recess located in the substrate, wherein the recess has an upper part and a lower part, and the minimum width of the upper part is larger than the maximum width of the lower part; and   a material located in the recess.   
     
     
         2 . The semiconductor structure according to  claim 1 , wherein the connecting point of the upper part and the lower part has a turning point. 
     
     
         3 . The semiconductor structure according to  claim 1 , wherein the sidewalls of the upper part and the lower part respectively comprise an upward-broadened oblique sidewall. 
     
     
         4 . The semiconductor structure according to  claim 3 , wherein the acute angle between the oblique sidewall of the upper part and a level is larger than the acute angle between the oblique sidewall of the lower part and a level. 
     
     
         5 . The semiconductor structure according to  claim 4 , wherein the acute angle between the oblique sidewall of the upper part and a level is larger than 89°. 
     
     
         6 . The semiconductor structure according to  claim 1 , wherein the sidewall of the upper part is essentially vertical to a level. 
     
     
         7 . The semiconductor structure according to  claim 1 , wherein the material comprises oxide. 
     
     
         8 . The semiconductor structure according to  claim 1 , wherein the recess comprises a first predetermined depth and the upper part comprises a second predetermined depth. 
     
     
         9 . The semiconductor structure according to  claim 8 , wherein the first predetermined depth is 2000 angstroms and the second predetermined depth is 400 angstroms. 
     
     
         10 . The semiconductor structure according to  claim 8 , wherein the material fills a part of the recess below a third predetermined depth. 
     
     
         11 . The semiconductor structure according to  claim 10 , wherein the second predetermined depth is larger than the third predetermined depth. 
     
     
         12 . The semiconductor structure according to  claim 11 , wherein the first predetermined depth is 2000 angstroms, the second predetermined depth is 400 angstroms and the third predetermined depth is 250 angstroms. 
     
     
         13 . A semiconductor process, comprising:
 providing a substrate;   forming a recess in the substrate, wherein the recess has a first sidewall;   filling a material in the recess and exposing a part of the recess; and   performing an etching process to laterally etch the exposing part of the recess, therefore the recess comprises an upper part and a lower part, wherein the upper part has a second sidewall and the lower part has the first sidewall.   
     
     
         14 . The semiconductor process according to  claim 13 , wherein the connecting point of the upper part and the lower part has a turning point. 
     
     
         15 . The semiconductor process according to  claim 13 , wherein the first sidewall and the second sidewall are upward-broadened oblique sidewalls. 
     
     
         16 . The semiconductor process according to  claim 15 , wherein the acute angle between the second sidewall and a level is larger than the acute angle between the first sidewall and a level. 
     
     
         17 . The semiconductor process according to  claim 16 , wherein the acute angle between the second sidewall and a level is larger than 89°. 
     
     
         18 . The semiconductor process according to  claim 13 , wherein the second sidewall is essentially vertical to a level. 
     
     
         19 . The semiconductor process according to  claim 13 , wherein the recess has a first predetermined depth, and the part of the recess and the upper part have a second predetermined depth. 
     
     
         20 . The semiconductor process according to  claim 19 , wherein the first predetermined depth is 2000 angstroms and the second predetermined depth is 400 angstroms. 
     
     
         21 . The semiconductor process according to  claim 19 , wherein the steps of filling the material in the recess comprise:
 filling the material until the material is higher than the second predetermined depth; and   etching back the material until exposing the part of the recess with the second predetermined depth.   
     
     
         22 . The semiconductor process according to  claim 19 , after performing the etching process, further comprising:
 filling the material in the recess until exposing a part of the recess with a third predetermined depth.   
     
     
         23 . The semiconductor process according to  claim 22 , wherein the second predetermined depth is larger than the third predetermined depth. 
     
     
         24 . The semiconductor process according to  claim 23 , wherein the first predetermined depth is 2000 angstroms, the second predetermined depth is 400 angstroms and the third predetermined depth is 250 angstroms. 
     
     
         25 . The semiconductor process according to  claim 13 , wherein the etching process comprises a dry etching process. 
     
     
         26 . The semiconductor process according to  claim 25 , wherein the dry etching process comprises a tetrafluoromethane, helium and oxygen containing dry etching process.

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