US2013086366A1PendingUtilityA1

Register File with Embedded Shift and Parallel Write Capability

39
Individually held — no corporate assignee on recordPriority: Sep 30, 2011Filed: Sep 30, 2011Published: Apr 4, 2013
Est. expirySep 30, 2031(~5.2 yrs left)· nominal 20-yr term from priority
Inventors:Aaron Douglass Lamb
G06F 9/30032G06F 9/30141
39
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Claims

Abstract

An apparatus includes a register file including a logical circuit. The register file is configured to perform one or more logical operations in conjunction with the logical circuit. The logical operation is performed in response to the register file receiving a register file control instruction. The register file control instruction is independent from an arithmetic logic unit (ALU) control instruction and a multiply-and-accumulate unit (MACU) control instruction.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus comprising:
 a register file including a logical circuit, the register file configured to perform at least one logical operation in conjunction with the logical circuit in response to the register file receiving a register file control instruction.   
     
     
         2 . The apparatus of  claim 1 , in which the at least one logical operation is one of: and, or, xor, shift, rotate, bit reverse and invert. 
     
     
         3 . The apparatus of  claim 1 , in which the logical circuit comprises a multiplexer, the multiplexer configured to facilitate performance of the logical operation, the multiplexer being independent from an arithmetic logic unit (ALU) and a multiply-and-accumulate unit (MACU). 
     
     
         4 . The apparatus of  claim 1 , in which the register file is configured to perform the at least one logical operation on a plurality of data words in parallel. 
     
     
         5 . The apparatus of  claim 1 , in which the register file is configured to perform logical operations in parallel with operations being performed by one of an arithmetic logic unit (ALU) and a multiply-and-accumulate unit (MACU). 
     
     
         6 . The apparatus of  claim 1 , in which the register control instruction is based on one of a time multiplexed instruction, an operand that controls select lines of a multiplexer, an opcode and flip flops that control the select lines of multiplexers. 
     
     
         7 . The apparatus of  claim 1 , in which the register file is configured to perform an operation independent from an arithmetic logic unit (ALU) and a multiply-and-accumulate unit (MACU) control, the operation being performed in one of every plurality of clock cycles. 
     
     
         8 . The apparatus of  claim 1 , in which the at least one logical operation comprises a plurality of same logical operations performed during multiple clock cycles in response to the register file control instruction. 
     
     
         9 . The apparatus of  claim 1 , in which the register file control instruction is independent from an arithmetic logic unit control instruction and a multiply-and-accumulate unit control instruction. 
     
     
         10 . The apparatus of  claim 1 , integrated into at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit. 
     
     
         11 . A method comprising:
 receiving a register file control instruction; and   performing at least one logical operation in conjunction with a logical circuit of a register file in response to the register file receiving the register file control instruction.   
     
     
         12 . The method of  claim 11 , in which performing at least one logical operation comprises performing one of anding, oring, xoring, shifting, rotating, bit reversing and inverting. 
     
     
         13 . The method of  claim 11 , further comprising performing the at least one logical operation by the register file on a plurality of data words in parallel. 
     
     
         14 . The method of  claim 11 , further comprising performing logical operations in parallel with operations being performed by one of an arithmetic logic unit (ALU) and a multiply-and-accumulate unit (MACU). 
     
     
         15 . The method of  claim 11 , further comprising performing an operation independent from an arithmetic logic unit (ALU) and a multiply-and-accumulate unit (MACU) control, the operation being performed on one of every plurality of clock cycles. 
     
     
         16 . The method of  claim 11 , The apparatus of  claim 1 , in which the at least one logical operation comprises a plurality of same logical operations performed during multiple clock cycles in response to the register file control instruction. 
     
     
         17 . The method of  claim 11 , further comprising executing the logical operation in at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit. 
     
     
         18 . An apparatus comprising:
 means for storing information in a processor including a logical circuit, the storing means configured to perform at least one logical operation in conjunction with the logical circuit in response to the storing means receiving a control instruction; and   means for processing results of the logical operation, the processing means being coupled to the storing means.   
     
     
         19 . The apparatus of  claim 18 , integrated into at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit. 
     
     
         20 . A computer program product, comprising:
 a computer-readable medium having non-transitory program code recorded thereon, the program code comprising:   program code to receive a register file control instruction; and   program code to perform at least one logical operation in conjunction with a logical circuit of a register file in response to the register file receiving the register file control instruction.   
     
     
         21 . The computer program product of  claim 20 , integrated into at least one of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

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