System and method of test mode gate operation

Abstract

A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a circuit includes a combinational logic portion including a logic path including a test isolation gate between a starting element and an ending element. The logic path includes at least a first gate element between the starting element and the test isolation gate. The logic path also includes at least a second gate element between the test isolation gate and the ending element. The starting element and the ending element are coupled to be tested via a scan chain test process during a test mode. In the test mode, an output of the second gate element is fixed at a constant logic level.

What is claimed is:  
     
         1 . An apparatus comprising:
 a circuit comprising a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element;   wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate;   wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element;   rein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode; and   wherein, in the test mode, an output of the second gate element is fixed at a constant logic level.   
     
     
         2 . The apparatus of  claim 1 , wherein the test isolation gate is configured to block an input of the second gate element from changing during the test mode. 
     
     
         3 . The apparatus of  claim 1 , further comprising a test enable input to receive a test enable signal, and wherein the test isolation gate is responsive to the test enable signal. 
     
     
         4 . The apparatus of  claim 1 , further comprising multiple combinational logic portions and multiple test isolation gates. 
     
     
         5 . The apparatus of  claim 1 , wherein, in the test mode, an output of the first gate element is responsive to a change in a first input to the first gate element. 
     
     
         6 . The apparatus of  claim 1 , wherein the test isolation gate is determined by a information related to a design of the circuit. 
     
     
         7 . The apparatus of  claim 1 , wherein the circuit is integrated in at least one semiconductor die. 
     
     
         8 . The apparatus of  claim 1 , further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the circuit is integrated. 
     
     
         9 . A method comprising:
 receiving design information representing at least one physical property of a semiconductor device, the semiconductor device including a memory and a circuit comprising:
 a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element; 
 wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate; 
 wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element; 
 wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode; and 
 wherein, in the test mode, an output of the second gate element is fixed at a constant logic level; 
   transforming the design information to comply with a file format; and   generating a data file including the transformed design information.   
     
     
         10 . The method of  claim 9 , wherein the data file includes a GDSII format, 
     
     
         11 . A method comprising:
 receiving a data file including design information corresponding to a semiconductor device; and   fabricating the semiconductor device according to the design information, wherein the semiconductor device includes:
 a circuit comprising:
 a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element; 
 wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate; 
 where the logic path further comprises at least a second gate element between the test isolation gate and the ending element; 
 wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode; and 
 wherein, in the test mode, an output of the second gate element is fixed at a constant logic level. 
 
   
     
     
         12 . The method of  claim 11 , wherein tire data file has a GDSII format. 
     
     
         13 . A method comprising:
 receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a semiconductor structure comprising:
 a circuit comprising:
 a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element; 
 wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate; 
 wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element; 
 wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode; and 
 wherein, in the test mode, an output of the second gate element is fixed at a constant logic level; and 
 
   transforming the design information to generate a data file.   
     
     
         14 . The method of  claim 13 , wherein the data file has a GERBER format. 
     
     
         15 . A method comprising:
 receiving a data file including design information including physical positioning information of a packaged semiconductor device on a circuit board; and   manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises:
 a circuit comprising:
 a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element; 
 wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate; 
 wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element; 
 wherein the starting element and the ending clement are coupled to be tested via a scan chain test process during a test mode; and 
 wherein, in the test mode, an output of the second gate element s fixed at a constant logic level. 
 
   
     
     
         16 . The method of  claim 15 , wherein the data file has a GERBER format. 
     
     
         17 . The method of  claim 15 , further comprising integrating the circuit board into a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communication device, a personal digital assistant (PDA), a fixed location data unit, and a computer. 
     
     
         18 . An apparatus comprising:
 a circuit comprising a combinational logic portion comprising a logic path comprising means for receiving a test isolation signal, wherein the means for receiving the test isolation signal is coupled between a starting element and an ending element;   wherein the logic path comprises at least a first gate element between the starting element and the means for receiving the test isolation signal;   wherein the logic path further comprises at least a second gate element between the means for receiving the test isolation signal and the ending element;   wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode; and   wherein, in the test mode, an output of the second gate element is fixed at a constant logic level.   
     
     
         19 . The apparatus of  claim 18 , wherein the means for receiving the test isolation signal is configured to block an input of the second gate element from changing during the test mode. 
     
     
         20 . A computer readable non-transitory medium storing a. data file including design information corresponding to a semiconductor device, wherein the semiconductor device includes:
 a circuit comprising:
 a combinational logic portion comprising a logic path comprising a test isolation gate between a starting element and an ending element; 
 wherein the logic path comprises at least a first gate element between the starting element and the test isolation gate; 
 wherein the logic path further comprises at least a second gate element between the test isolation gate and the ending element; 
 wherein the starting element and the ending element are coupled to be tested via a scan chain test process during a test mode; and 
 wherein, in the test mode, an output of the second gate element is fixed at a constant logic level. 
   
     
     
         21 . The computer readable non-transitory medium of  claim 20 , wherein the data file has a GDSII format.