Semiconductor memory circuit and control method for reading data

Abstract

A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a plurality of memory circuits that connect to a first bit line, a second bit line, and a word line and that hold information;   a pre-charge control circuit that connects to a first pre-charge control line, the first bit line, and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line; and a first read control circuit having a first transistor that has a source terminal connected to a power supply and a gate terminal connected to a read-column selection line; a second transistor that has a source terminal connected to a drain terminal of the first transistor, a gate terminal connected to the first bit line, and a drain terminal connected to a first global-bit-line driver control line and that charges the first global-bit-line driver control line on the basis of the input from the read-column selection line and the potential level of the first bit line; a third transistor that has a drain terminal connected to the global-bit-line driver control line, a gate terminal connected to the read-column selection line, and a source terminal grounded; and a fourth transistor that has a drain terminal connected to a third bit line, a gate terminal connected to the first global-bit-line driver control line, and a source terminal grounded, wherein the column having the first bit line and the second bit line is thus selected on the basis of the input from the pre-charged first global-bit-line driver control line, the fourth transistor is brought into conduction, and the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits is output to the third bit line; and   a second read control circuit having a fifth transistor that has a source terminal connected to a power supply and a gate terminal connected to a read-column selection line; and a sixth transistor that has a source terminal connected to a drain terminal of the fifth transistor, a gate terminal connected to the second bit line, and a drain terminal connected to a second global-bit-line driver control line and, that charges the second global-bit-line driver control line on the basis of the input from the second read-column selection line and the potential level of the second bit line; a seventh transistor that has a drain terminal connected to the global-bit-line driver control line, a gate terminal connected to the second read-column selection line, and a source terminal grounded and that pre-discharges the global-bit-line driver control line on the basis of column selection signal; and an eighth transistor that has a drain terminal connected to a fourth bit line, a gate terminal connected to the second global-bit-line driver control line, and a source terminal grounded, wherein the eighth transistor is brought into conduction on the basis of the input from the pre-charged second global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits is output to the fourth bit line.   
     
     
         2 . A control method for reading data in a semiconductor memory device, the semiconductor memory device having:
 a plurality of memory circuits that connect to a first bit line, a second bit line, and a word line and that hold information;   a pre-charge control circuit that connects to a first pre-charge control line, the first bit line, and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line; and   a first read control circuit having a first transistor that has a source terminal connected to a power supply and a gate terminal connected to a read-column selection line; a second transistor that has a source terminal connected to a drain terminal of the first transistor, a gate terminal connected to the first bit line, and a drain terminal connected to a first global-bit-line driver control line and that charges the first global-bit-line driver control line on the basis of the input from the read-column selection line and the potential level of the first bit line; a third transistor that has a drain terminal connected to the global-bit-line driver control line, a gate terminal connected to the read-column selection line, and a source terminal grounded; and a fourth transistor that has a drain terminal connected to a third bit line, a gate terminal connected to the first global-bit-line driver control line, and a source terminal grounded, wherein the fourth transistor is brought into conduction on the basis of the input from the charged first global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in a memory circuit connecting to the driven word line among the plurality of memory circuits is output to the third bit line; and   a second read control circuit having a fifth transistor that has a source terminal connected to a power supply and a gate terminal connected to a read-column selection line; and a sixth transistor that has a source terminal connected to a drain terminal of the fifth transistor, a gate terminal connected to the second bit line, and a drain terminal connected to a second global-bit-line driver control line and, on the basis of the input from the second read-column selection line and the potential level of the second bit line, that charges the second global-bit-line driver control line; a seventh transistor that has a drain terminal connected to the global-bit-line driver control line, a gate terminal connected to the second read-column selection line, and a source terminal grounded; and an eighth transistor that has a drain terminal connected to a fourth bit line, a gate terminal connected to the second global-bit-line driver control line, and a source terminal grounded, wherein the eighth transistor is brought into conduction on the basis of the input from the charged second global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits is output to the fourth bit line, the control method for reading data comprising:   selecting the column having the first bit line and the second bit line by bringing the fourth transistor into conduction on the basis of the input from the charged first global-bit-line driver control line;   reading the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits from the third bit line;   selecting the column having the first bit line and the second bit line by bringing the eighth transistor into conduction on the basis of the input from the charged second global-bit-line driver control line; and   reading the information held in the memory circuit connecting to the driven word line among the plurality of memory circuits to the fourth bit line.