Ic layout pattern matching and classification system and method

Abstract

A system and method for restricting the number of layout patterns by pattern identification, matching and classification, includes decomposing the pattern windows into a low frequency component and a high frequency component using a wavelet analysis for an integrated circuit layout having a plurality of pattern windows. Using the low frequency component as an approximation, a plurality of moments is computed for each pattern window. The pattern windows are classified using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows.

What is claimed is: 
     
         1 . A method for classifying patterns in a set of layout patterns, comprising:
 computing a plurality of moments for each of a plurality of pattern windows of an integrated circuit layout using a low frequency component of a wavelet analysis as an approximation; and   classifying the pattern windows into pattern classes using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows.   
     
     
         2 . The method as recited in  claim 1 , wherein the wavelet analysis includes decomposing the pattern windows using Haar wavelets. 
     
     
         3 . The method as recited in  claim 1 , wherein computing a plurality of moments for each pattern window includes computing one or more of a mean, a variance, a skewness and a kurtosis. 
     
     
         4 . The method as recited in  claim 1 , wherein classifying the pattern windows using a distance computation includes classifying the pattern windows using a Canberra metric. 
     
     
         5 . The method as recited in  claim 1 , further comprising computing the moments for a plurality of levels, and the step of classifying the pattern windows using a distance computation for respective moments of the pattern windows includes classifying the pattern windows using a distance computation for respective moments of the pattern windows in the plurality of levels. 
     
     
         6 . The method as recited in  claim 5 , wherein the levels include frequency components in one or more orientations. 
     
     
         7 . The method as recited in  claim 6 , wherein the orientations include one or more of horizontal, vertical and diagonal. 
     
     
         8 . The method as recited in  claim 1 , wherein classifying reveals a set of patterns for inclusion in a permissible set of patterns for a given technology node. 
     
     
         9 . The method as recited in  claim 1 , further comprising reducing the set of layout patterns by identifying, matching and classifying the patterns into functional equivalence classes. 
     
     
         10 . A computer readable storage medium comprising a computer readable program for classifying patterns in a set of layout patterns, wherein the computer readable program when executed on a computer causes the computer to perform steps of as recited in  claim 1 . 
     
     
         11 . An integrated circuit chip configured to perform a method for classifying patterns in a set of layout patterns, the method as recited in  claim 1 .