US2013070513A1PendingUtilityA1

Method and apparatus for direct backup of memory circuits

Individually held — no corporate assignee on recordPriority: Sep 16, 2011Filed: Jul 30, 2012Published: Mar 21, 2013

Est. expirySep 16, 2031(~5.1 yrs left)· nominal 20-yr term from priority

Inventors:Donald R. Weiss John Wuu

H03K 19/0016G11C 13/0002H03K 19/0019G11C 11/4125G11C 14/0045G11C 5/005

PatentIndex Score

Cited by

References

Claims

Abstract

An integrated circuit employs at least one active memory circuit and at least one memory state backup circuit wherein the at least one memory state backup circuit includes at least one passive variable resistance memory cell and at least one passive variable resistance memory cell interface that are used to backup data from the active memory circuit to the PVRM cell. Data is then placed back into the active memory circuit from the PVRM cell during a restore operation. The PVRM cell interface is operative to read the PVRM cell in response to a restore signal. PVRM cell interface control logic is operative to remove power to the PVRM cell after backup of the data to the PVRM cell from the active memory circuit. A PVRM cell (e.g., a bit cell) is added to each memory circuit that stores state information on an integrated circuit.

Claims

exact text as granted — not AI-modified

What is claimed is: 
     
         1 . An integrated circuit comprising:
 at least one active memory circuit; and   at least one memory state backup circuit, operatively coupled to the active memory circuit, comprising:
 at least one passive variable resistance memory (PVRM) cell; and 
 at least one PVRM cell interface operatively coupled to the active memory circuit and to the PVRM cell and operative to back up data to the PVRM cell from the active memory circuit. 
   
     
     
         2 . The integrated circuit of  claim 1  wherein the PVRM cell interface is operative to read the PVRM cell in response to a restore signal. 
     
     
         3 . The integrated circuit of  claim 1  comprising PVRM cell interface control logic operative to remove power to the PVRM cell after back up of the data to the PVRM cell. 
     
     
         4 . The integrated circuit of  claim 2  comprising a restore switch, operatively coupled to an input of the active memory circuit and to an output of the PVRM interface, that is responsive to a restore signal to cause the backup data to be input to the active memory circuit; and
 a save switch operatively coupled to an output of the active memory circuit and to an input of the PVRM interface, that is responsive to a back up signal to pass data from the active memory circuit to be stored in the PVRM cell. 
 
     
     
         5 . The integrated circuit of  claim 2  comprising:
 a restore switch, operatively coupled to an input of the active memory circuit and to an output of the PVRM interface, that is responsive to a restore signal to cause the backup data to be input to the active memory circuit; and 
 a save switch, operatively coupled to an output of the active memory circuit and to an input of the PVRM interface, that is operative to automatically select output data from the active memory circuit in response to output data being stored by the active memory circuit. 
 
     
     
         6 . The integrated circuit of  claim 4  wherein the active memory circuit comprises a flip flop comprised of a master latch serially connected to a slave latch and wherein the output of the active memory circuit is an output of the slave latch and wherein the input of the active memory circuit is an input of the master latch. 
     
     
         7 . An integrated circuit comprising:
 an active memory circuit comprising an active master latch stage and a passive variable resistance memory (PVRM) slave latch stage operatively coupled to an output of the active master latch stage.   
     
     
         8 . The integrated circuit of  claim 7  comprising a switch interposed between the active master latch stage and a passive variable resistance memory (PVRM) slave latch stage, and wherein the PVRM slave latch stage comprises a PVRM cell interface coupled to the switch and a PVRM cell coupled to the PVRM cell interface, such that the PVRM slave stage stores data output from the active master latch in response to clocking of the switch and wherein the PVRM stage stores data in a non-volatile manner. 
     
     
         9 . The integrated circuit of  claim 8  comprising a clock circuit operatively coupled to an input of the switch to provide the clocking of the switch for the PVRM slave stage. 
     
     
         10 . The integrated circuit of  claim 1  comprising a plurality of active memory circuits and a plurality of passive variable resistance memory (PVRM) cells that form a PVRM cell array, and wherein the PVRM cell interface is operative to control reads and writes to each of the PVRM cells to facilitate data backup from the plurality of active memory circuits. 
     
     
         11 . A method for providing state backup in an integrated circuit comprising:
 latching data in a active memory circuit;   controlling a corresponding passive variable resistance memory (PVRM) cell to backup the latched data in a non-volatile manner;   powering off the active memory circuit;   powering off the PVRM cell;   powering on the active memory circuit;   powering on the PVRM cell; and   restoring data in the active memory circuit using the backup data in the PVRM cell.   
     
     
         12 . The method of  claim 11  wherein controlling a corresponding passive variable resistance memory (PVRM) cell to backup the latched data in a non-volatile manner comprises:
 generating a save signal to control reading of data from the active memory circuit to be stored in the PVRM cell; and wherein 
 restoring data in the active memory circuit using the backup data in the PVRM cell comprises generating a restore signal to cause the backup data from the PVRM cell to be input to the active memory circuit. 
 
     
     
         13 . An apparatus comprising:
 a display; and   an integrated circuit operative to provide data for output on the display comprising:
 at least one active memory circuit; and 
 at least one memory state backup circuit, operatively coupled to the active memory circuit, comprising:
 at least one passive variable resistance memory (PVRM) cell; and 
 at least one PVRM cell interface operatively coupled to the active memory circuit and to the PVRM cell and operative to back up data to the PVRM cell from the active memory circuit. 
 
   
     
     
         14 . The apparatus of  claim 13  wherein the PVRM cell interface is operative to read the PVRM cell in response to a restore signal. 
     
     
         15 . The apparatus of  claim 13  wherein the IC comprises PVRM cell interface control logic operative to remove power to the PVRM cell after back up of the data to the PVRM cell. 
     
     
         16 . The apparatus of  claim 14  wherein the IC comprises a restore switch, operatively coupled to an input of the active memory circuit and to an output of the PVRM interface, that is responsive to a restore signal to cause the backup data to be input to the active memory circuit; and a save switch operatively coupled to an output of the active memory circuit and to an input of the PVRM interface, that is responsive to a back up signal to pass data from the active memory circuit to be stored in the PVRM cell. 
     
     
         17 . The apparatus of  claim 14  wherein the IC comprises:
 a restore switch, operatively coupled to an input of the active memory circuit and to an output of the PVRM interface, that is responsive to a restore signal to cause the backup data to be input to the active memory circuit; and 
 a save switch, operatively coupled to an output of the active memory circuit and to an input of the PVRM interface, that is operative to automatically select output data from the active memory circuit in response to output data being stored by the active memory circuit. 
 
     
     
         18 . A non-transitory computer readable medium comprising executable instructions that when executed by an integrated circuit fabrication system, causes the integrated circuit fabrication system to produce an integrated circuit that comprises:
 at least one active memory circuit; and   at least one memory state backup circuit, operatively coupled to the active memory circuit, comprising:
 at least one passive variable resistance memory (PVRM) cell; and 
 at least one PVRM cell interface operatively coupled to the active memory circuit and to the PVRM cell and operative to back up data to the PVRM cell from the active memory circuit. 
   
     
     
         19 . The computer readable medium of  claim 18  comprising executable instructions that when executed by the integrated circuit fabrication system, causes the integrated circuit fabrication system to produce an integrated circuit that produces the PVRM cell interface to be operative to read the PVRM cell in response to a restore signal. 
     
     
         20 . The computer readable medium of  claim 18  comprising executable instructions that when executed by an integrated circuit fabrication system, causes the integrated circuit fabrication system to produce an integrated circuit that comprises PVRM cell interface control logic operative to remove power to the PVRM cell after back up of the data to the PVRM cell.

Join the waitlist — get patent alerts

Track US2013070513A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.