Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device includes a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall, and a second transistor that includes a second gate insulating film, a second gate electrode, a source and a drain region, and a second sidewall. The first transistor includes a portion of a logic circuit. The second transistor includes a transistor included in a memory cell of a DRAM, or includes a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM. The first gate insulating film has a same thickness as that of the second gate insulating film. The first gate electrode has the same thickness as that of the second gate electrode. A layer structure of the first sidewall is a same as a layer structure of the second sidewall.

1 . A semiconductor device, comprising:
 a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall; and   a second transistor, formed in the substrate, that includes a second gate insulating film, a second gate electrode, a source and a drain region, and a second sidewall,   wherein the first transistor comprises a portion of a logic circuit,   wherein the second transistor comprises a transistor included in a memory cell of a Dynamic Random Access Memory (DRAM), or comprises a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM,   wherein the first gate insulating film has a same thickness as that of the second gate insulating film,   wherein the first gate electrode has a same thickness as that of the second gate electrode, and   wherein a layer structure of the first sidewall is a same as a layer structure of the second sidewall such that a width of the second sidewall is larger than a width of the first sidewall.   
     
     
         2 . The semiconductor device as set forth in  claim 1 , wherein the first sidewall and the second sidewall include:
 a first insulating film formed over the substrate and over a sidewall of the first gate electrode or the second gate electrode;   a second insulating film formed over the first insulating film; and   a concave portion provided in an end surface of the first insulating film which is located over the substrate, and   wherein a concave portion of the first sidewall is deeper than a concave portion of the second sidewall,   the semiconductor device further comprising:
 an etching stopper film, formed over the first transistor and the second transistor, of which a portion intrudes into the concave portion of each of the first sidewall and the second sidewall; and 
 an insulating interlayer located over the etching stopper film. 
   
     
     
         3 . The semiconductor device as set forth in  claim 2 , wherein the etching stopper film comprises one of TEOS, SiO 2 , SiN, SiON, HDP, PSG, NSG, and BPSG. 
     
     
         4 . The semiconductor device as set forth in  claim 1 , further comprising:
 an etching stopper film formed over the first transistor and the second transistor;   an insulating interlayer located over the etching stopper film; and   a contact which is formed in the insulating interlayer and the etching stopper film, and connected to the source and the drain region of the first transistor,   wherein at least a surface layer of the first sidewall comprises a material different from that of the etching stopper film.   
     
     
         5 . The semiconductor device as set forth in  claim 4 , wherein the etching stopper film comprises a silicon nitride film, and
 wherein at least the surface layer of the first sidewall comprises a silicon oxide film.   
     
     
         6 . The semiconductor device as set forth in  claim 5 , wherein the first sidewall includes a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in that order. 
     
     
         7 . The semiconductor device as set forth in  claim 1 , further comprising:
 an device isolation film which is buried in the substrate, and is located between the logic circuit and the memory cell;   a gate interconnect which is formed over the device isolation film, and is connected to the second gate electrode;   a silicide film formed over the gate interconnect; and   a groove, formed in the device isolation film, that extends in a direction intersecting the gate interconnect.   
     
     
         8 . The semiconductor device as set forth in  claim 1 , wherein the width of the first sidewall is equal to or greater than 1 nm and equal to or less than 70 nm, and the width of the second sidewall is equal to or greater than 1.4 nm and equal to or less than 100 nm. 
     
     
         9 . A semiconductor device, comprising:
 a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode and a first sidewall;   a second transistor, formed in the substrate, that includes a second gate insulating film, a source and a drain region, a second gate electrode and a second sidewall,   wherein the first gate insulating film has a same thickness as that of the second gate insulating film,   wherein the first gate electrode has a same thickness as that of the second gate electrode, and   wherein a layer structure of the first sidewall is a same as a layer structure of the second sidewall such that a width of the second sidewall is larger than a width of the first sidewall.   
     
     
         10 . A semiconductor device according to  claim 9 , wherein the first transistor comprises a portion of a logic circuit, and
 wherein the second transistor comprises a transistor included in a memory cell, or comprises a portion of a peripheral circuit that performs writing and erasing with respect to the memory cell.   
     
     
         11 . A semiconductor device according to  claim 10 , wherein the memory cell comprises a memory cell of a Dynamic Random Access Memory (DRAM). 
     
     
         12 . A semiconductor device according to  claim 9 , wherein the first sidewall and the second sidewall include:
 a first insulating film formed over the substrate and over a sidewall of the first gate electrode or the second gate electrode;   a second insulating film formed over the first insulating film; and   a concave portion provided in an end surface of the first insulating film which is located over the substrate, and   wherein a concave portion of the first sidewall is deeper than a concave portion of the second sidewall,   the semiconductor device further comprising:
 an etching stopper film, formed over the first transistor and the second transistor, of which a portion intrudes into the concave portion of each of the first sidewall and the second sidewall; and 
 an insulating interlayer located over the etching stopper film. 
   
     
     
         13 . A semiconductor device according to  claim 12 , wherein the etching stopper film comprises one of TEOS, SiO 2 , SiN, SiON, HDP, PSG, NSG, and BPSG. 
     
     
         14 . A semiconductor device according to  claim 9 , further comprising:
 an etching stopper film formed over the first transistor and the second transistor;   an insulating interlayer located over the etching stopper film; and   a contact which is formed in the insulating interlayer and the etching stopper film, and connected to the source and the drain region of the first transistor,   wherein at least a surface layer of the first sidewall comprises a material different from that of the etching stopper film.   
     
     
         15 . A semiconductor device according to  claim 14 , wherein the etching stopper film comprises a silicon nitride film, and
 wherein at least the surface layer of the first sidewall comprises a silicon oxide film.   
     
     
         16 . A semiconductor device according to  claim 15 , wherein the first sidewall includes a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in that order. 
     
     
         17 . A semiconductor device according to  claim 9 , further comprising:
 an device isolation film which is buried in the substrate, and is located between the logic circuit and the memory cell;   a gate interconnect which is formed over the device isolation film, and is connected to the second gate electrode;   a silicide film formed over the gate interconnect; and   a groove, formed in the device isolation film, that extends in a direction intersecting the gate interconnect.   
     
     
         18 . A semiconductor device according to  claim 9 , wherein the width of the first sidewall is equal to or greater than 1 nm and equal to or less than 70 nm, and the width of the second sidewall is equal to or greater than 1.4 nm and equal to or less than 100 nm. 
     
     
         19 . A method of manufacturing a semiconductor device, the method comprising:
 forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor, and a second gate insulating film and a second gate electrode of a second transistor;   forming an extension region of the first transistor and an extension region of the second transistor;   forming a first sidewall in a side wall of the first transistor;   forming a second sidewall having a larger width than that of the first sidewall in a sidewall of the second transistor; and   forming a source and a drain region in each of the first transistor and the second transistor,   wherein a layer structure of the first sidewall is a same as a layer structure of the second sidewall in the semiconductor device.   
     
     
         20 . A method of manufacturing a semiconductor device according to  claim 19 , wherein the first transistor comprises a portion of a logic circuit, and
 wherein the second transistor comprises a transistor included in a memory cell of a Dynamic Random Access Memory (DRAM), or comprises a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM.