Systems and Methods for Controlling the Use of Processing Algorithms, and Applications Thereof

Abstract

Embodiments provide systems and methods for controlling the use of processing algorithms, and applications thereof. In an embodiment, authorization to use an algorithm is validated in a system having a processor capable of executing user defined instructions, by executing a user defined instruction that writes a first value to a first storage of a user defined instruction block, uses the first value to transform a second value located in a second storage of the user defined instruction block, and compares the transformed second value to a third value located in a third storage. Use of the algorithm is permitted only if the comparison of the transformed second value to the third value indicates that use of the algorithm is authorized. In another embodiment, authorization to use an at least partially decrypted algorithm is validated via a key for enablement.

1 . A system that validates authorization to use an algorithm using a hardware processor, comprising:
 a first memory containing an encrypted portion of an algorithm;   a second memory;   a third memory that stores a key for enablement of the algorithm; and   decryption logic,   wherein the encrypted portion of the algorithm is loaded from the first memory into the second memory, decrypted using the decryption logic, and upon execution of the decrypted portion, an undocumented code is checked against the key during the decrypted portion's initialization in order to validate enablement of the algorithm.   
     
     
         2 . The system of  claim 1 , wherein the algorithm is an audio algorithm. 
     
     
         3 . The system of  claim 1 , wherein the third memory is read-only memory. 
     
     
         4 . The system of  claim 1 , wherein the second memory is instruction scratch pad memory. 
     
     
         5 . The system of  claim 1 , wherein if enablement is not validated, execution of the algorithm is stopped. 
     
     
         6 . The system of  claim 1 , further comprising core debug logic, wherein the core debug logic includes an architectural state bit that indicates no reading out of the second memory location by a debugger program. 
     
     
         7 . The system of  claim 1 , further comprising core debug logic, wherein the core debug logic includes an implementation-specific bit in a debug configuration register that indicates no reading out of the second memory location by a debugger program. 
     
     
         8 . A method of authorizing the use of an algorithm using a hardware processor, comprising:
 loading an encrypted portion of the algorithm from a first memory into a second memory;   decrypting the encrypted portion of the algorithm using decryption logic of the hardware processor, resulting in a decrypted portion of the algorithm;   executing the decrypted portion of the algorithm to check an undocumented code against an enablement key; and   authorizing use of the algorithm based on the executing of the decrypted portion of the algorithm.   
     
     
         9 . The method of  claim 8 , wherein loading the encrypted portion of the algorithm comprises loading an encrypted portion of an audio algorithm. 
     
     
         10 . The method of  claim 8 , wherein executing the decrypted portion of the algorithm to check the undocumented code against the enablement key comprises executing the decrypted portion of the algorithm to check an undocumented code against an enablement key stored in a read-only memory. 
     
     
         11 . The method of  claim 8 , wherein loading the encrypted portion of the algorithm from the first memory into the second memory comprises loading the encrypted portion of the algorithm from the first memory into a scratch pad memory. 
     
     
         12 . The method of  claim 8 , wherein authorizing use of the algorithm based on the executing of the decrypted portion of the algorithm comprises validating enablement of the algorithm, wherein execution of the algorithm is stopped if the enablement of the algorithm is not validated. 
     
     
         13 . The method of  claim 8 , further comprising using core debug logic having an architectural state bit to indicate no reading out of the second memory by a debugger program. 
     
     
         14 . The method of  claim 8 , farther comprising using core debug logic having an implementation-specific bit in a debug configuration register that indicates no reading out of the second memory location by a debugger program. 
     
     
         15 . A computer-readable storage medium having computer-executable instructions stored thereon that, when executed by a computing device, cause the computing device to perform operations for authorizing the use of an algorithm using a hardware processor, the operations comprising:
 loading an encrypted portion of the algorithm from a first memory into a second memory;   decrypting the encrypted portion of the algorithm using decryption logic of the hardware processor, resulting in a decrypted portion of the algorithm;   executing the decrypted portion of the algorithm to check an undocumented code against an enablement key; and   authorizing use of the algorithm based on the executing of the decrypted portion of the algorithm.