Method for fabricating a semiconductor structure

Abstract

A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; and performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value.

1 . A method for fabricating a semiconductor structure, comprising the steps of:
 providing a substrate;   depositing a material layer on the substrate;   forming at least one dielectric layer on the material layer;   forming a patterned resist on the dielectric layer;   performing a first trimming process on at least the patterned resist; and   performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value.   
     
     
         2 . The method of  claim 1 , wherein the material layer comprises silicon, polysilicon layer or metal. 
     
     
         3 . The method of  claim 1 , further comprising calculating a fixed time of the second trimming process after trimming greater than 70% of the total trimming value. 
     
     
         4 . The method of  claim 1 , wherein the at least one dielectric layer comprises a bottom anti-reflective coating (BARC) and a hard mask. 
     
     
         5 . The method of  claim 4 , further comprising:
 performing the first trimming process on the patterned resist;   using the patterned resist for etching the BARC;   performing the second trimming process on the patterned resist and the BARC;   using the patterned resist and the BARC to etch the hard mask for exposing the material layer;   performing a third trimming process on the BARC and the hard mask; and   using the BARC and the hard mask for etching the material layer.   
     
     
         6 . The method of  claim 4 , further comprising:
 performing the first trimming process on the patterned resist and the BARC;   using the patterned resist and the BARC to etch the hard mask for exposing the material layer;   performing the second trimming process on the BARC and the hard mask; and   using the BARC and the hard mask for etching the material layer.   
     
     
         7 . The method of  claim 1 , wherein the at least one dielectric layer comprises a dielectric anti-reflective coating (DARC), an advanced patterning film (APF), and a hard mask. 
     
     
         8 . The method of  claim 7 , further comprising:
 performing the first trimming process on the patterned resist and the DARC;   using the patterned resist and the DARC for etching the APF;   performing the second trimming process on the DARC and the APF; and   using the DARC and the APF to etch the hard mask for exposing the material layer; and   performing a third trimming process on the APF and the hard mask; and   using the APF and the hard mask for etching the material layer.   
     
     
         9 . The method of  claim 7 , further comprising:
 performing the first trimming process on the patterned resist and the DARC;   using the patterned resist and the DARC for etching the APF and the hard mask for exposing the material layer;   performing the second trimming process on the APF and the hard mask; and   using the APF and the hard mask for etching the material layer.   
     
     
         10 . The method of  claim 1 , wherein the second trimming process is conducted according to a fixed time for controlling the width difference between the top of the material layer and the bottom of the material layer no more than 10%. 
     
     
         11 . The method of  claim 1 , wherein the second trimming process is performed on at least the dielectric layer after exposing the material layer. 
     
     
         12 . A method for fabricating a semiconductor structure, comprising the steps of:
 providing a substrate;   depositing a material layer on the substrate;   forming at least one dielectric layer on the material layer;   forming a patterned resist on the dielectric layer;   performing a first trimming process on at least the patterned resist; and   performing a second trimming process on at least the dielectric layer after exposing the material layer.   
     
     
         13 . The method of  claim 12 , wherein the material layer comprises silicon, polysilicon layer or metal. 
     
     
         14 . The method of  claim 12  further comprising calculating a fixed time of the second trimming process after trimming greater than 70% of the total trimming value. 
     
     
         15 . The method of  claim 12 , wherein the at least one dielectric layer comprises a bottom anti-reflective coating (BARC) and a hard mask. 
     
     
         16 . The method of  claim 15 , further comprising:
 performing the first trimming process on the patterned resist;   using the patterned resist for etching the BARC;   performing the second trimming process on the patterned resist and the BARC;   using the patterned resist and the BARC to etch the hard mask for exposing the material layer;   performing a third trimming process on the BARC and the hard mask; and   using the BARC and the hard mask for etching the material layer.   
     
     
         17 . The method of  claim 15 , further comprising:
 performing the first trimming process on the patterned resist and the BARC;   using the patterned resist and the BARC to etch the hard mask for exposing the material layer;   performing the second trimming process on the BARC and the hard mask; and   using the BARC and the hard mask for etching the material layer.   
     
     
         18 . The method of  claim 12 , wherein the at least one dielectric layer comprises a dielectric anti-reflective coating (DARC), an advanced patterning film (APF), and a hard mask. 
     
     
         19 . The method of  claim 18 , further comprising:
 performing the first trimming process on the patterned resist and the DARC;   using the patterned resist and the DARC for etching the APF;   performing the second trimming process on the DARC and the APF; and   using the DARC and the APF to etch the hard mask for exposing the material layer; and   performing a third trimming process on the APF and the hard mask; and   using the APF and the hard mask for etching the material layer.   
     
     
         20 . The method of  claim 18 , further comprising:
 performing the first trimming process on the patterned resist and the DARC;   using the patterned resist and the DARC for etching the APF and the hard mask for exposing the material layer;   performing the second trimming process on the APF and the hard mask; and   using the APF and the hard mask for etching the material layer.   
     
     
         21 . The method of  claim 12 , wherein the second trimming process is conducted according to a fixed time for controlling the width difference between the top of the material layer and the bottom of the material layer no more than 10%.