Techniques for Impeding Reverse Engineering

Abstract

Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

1 . An anti-reverse engineering method for forming circuit blocks, the method comprising the steps of:
 forming a plurality of circuit blocks by the steps of:
 forming at least one first metal layer; 
 forming a plurality of vias in contact with the first metal layer; 
 forming at least one second metal layer that is in a contact position with one or more of the vias and in a non-contact position with one or more of the other vias, wherein the vias that are in a contact position with the second metal layer are true vias and the vias that are in a non-contact position with the second metal layer are false vias, 
   wherein the first metal layer, the second metal layer and the vias are in a same location and a same position relative to one another in each of the circuit blocks; and   varying, from at least one of the circuit blocks to at least one other of the circuit blocks, which of the vias are in a contact position with the second metal layer and which of the vias are in a non-contact position with the second metal layer so as to vary which of the vias are true vias and which of the vias are false vias.   
     
     
         2 . The method of  claim 1 , wherein the step of forming the plurality of circuit blocks comprises the step of:
 forming at least one NAND gate and at least one NOR gate.   
     
     
         3 . The method of  claim 1 , further comprising the steps of:
 depositing an insulating layer (a) over the first metal layer;   etching holes in the insulating layer (a); and   filling the holes with a conductor material to form the vias.   
     
     
         4 . The method of  claim 3 , wherein the insulating layer (a) comprises an oxide material. 
     
     
         5 . The method of  claim 3 , wherein the holes are etched in the insulating layer by reactive ion etching using the first metal layer as an etch stop. 
     
     
         6 . The method of  claim 3 , further comprising the step of:
 depositing an optically transparent etch stop film into one or more of the holes.   
     
     
         7 . The method of  claim 6 , wherein the optically transparent etch stop film comprises aluminum oxide. 
     
     
         8 . The method of  claim 3 , further comprising the step of:
 depositing an insulating layer (b) over the insulating layer (a), so as to cover the vias.   
     
     
         9 . The method of  claim 8 , further comprising the step of:
 forming the second metal layer in the insulating layer (b), by the steps of:
 selectively implanting ions in the insulating layer (b) so as to form at least one implant region over one or more of the vias, the implanted ions being configured to alter an etch rate through the insulating layer (b) within the implant region; 
 etching the insulating layer (b) to, at the same time, form a pattern for the second metal layer both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer (b) within the implant region is different from an etch rate through the insulating layer (b) outside of the implant region, and wherein the etch is performed for an amount of time needed to either etch completely through the insulating layer (b) within the implant region or etch completely through the insulating layer (b) outside of the implant region; and 
 filling the pattern with a conductor material to form the second metal layer. 
   
     
     
         10 . The method of  claim 9 , further comprises the step of:
 selectively implanting argon ions in the insulating layer (b) so as to form the implant region within the insulating layer (b), the implanted argon ions being selected to enhance an etch rate through the insulating layer (b) within the implant region.   
     
     
         11 . The method of  claim 9 , further comprising the step of:
 selectively implanting nitrogen ions in the insulating layer (b) so as to form the implant region within the insulating layer (b), the implanted nitrogen ions being selected to reduce the etch rate through the insulating layer (b) within the implant region.