Semiconductor Device

Abstract

A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

1 . A semiconductor device having a plurality of first MISFETs arranged in a first direction and a plurality of second MISFETs arranged in the first direction,
 wherein each of the first MISFETs comprises:   a first gate insulating film formed over a semiconductor substrate;   a first gate electrode formed over the first gate insulating film; and   a first impurity region formed in the semiconductor substrate, the first impurity region positioned adjacent to the first gate electrode;   wherein each of the second MISFETs comprises:   a second gate insulating film formed over the semiconductor substrate;   a second gate electrode formed over the second gate insulating film; and   the first impurity region formed between the first gate electrode and the second gate electrode, the first impurity region being in common between each of the first MISFETs and the second MISFETs arranged adjacent in a second direction perpendicular to the first direction,   wherein the first gate and the second gate are formed in a sidewall form,   wherein the first gate electrodes extends in the first direction such that the first gate is common to each of the first MISFETs that are adjacent to one another in the first direction,   wherein the second gate electrodes extends in the first direction such that the second gate is common to each of the second MISFETs that are adjacent to one another in the first direction,   wherein, in the first MISFETs and the second MISFETs, the first gate electrode and the second gate electrode are not electrically connected and are capable of being applied with a gate signal independently,   wherein a plurality of the second impurity regions are formed in the semiconductor substrate and arranged in the first direction, and   wherein adjacent first impurity regions of the first MISFETs and the second MISFETs are electrically connected by an intervening one of the second impurity regions.   
     
     
         2 . A semiconductor device according to the  claim 1 ,
 wherein the first gate insulating film and the second gate insulating film include a charge storage film respectively.   
     
     
         3 . A semiconductor device according to the  claim 2 ,
 wherein the charge storage film is comprised of a silicon nitride film.   
     
     
         4 . A semiconductor device according to the  claim 1 ,
 wherein metal silicide films are formed over each of the first impurity regions of the first MISFETs and the second MISFETs.   
     
     
         5 . A semiconductor device according to the  claim 1 ,
 wherein the second impurity regions are formed on a surface of the semiconductor substrate.   
     
     
         6 . A semiconductor device according to the  claim 1 ,
 wherein the second impurity regions are formed on a surface of the semiconductor substrate.