Devices and methods to improve carrier mobility

Abstract

Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the silicon channel, where the silicon channel is configured to conduct current under appropriate operating conditions of the semiconductor device.

1 . A method comprising:
 forming a source and a drain of a transistor, the source and drain separated by a silicon channel;   forming a gate stack on the silicon channel; and   forming a first silicon oxynitride layer as part of a first spacer by chemical vapor deposition at a temperature greater than 750° C., the first spacer disposed adjacent the gate stack and on a portion of the drain; and   forming a second silicon oxynitride layer as part of a second spacer by chemical vapor deposition at a temperature greater than 750° C., the second spacer disposed adjacent the gate stack and on a portion of the source, the first and second silicon oxynitride layers structured to control strain in the silicon channel.   
     
     
         2 . The method of  claim 1 , wherein the method includes forming the first spacer substantially as the first silicon oxynitride layer and forming the second spacer substantially as the second silicon oxynitride layer. 
     
     
         3 . The method of  claim 1 , wherein forming a gate stack includes forming a gate dielectric on the silicon channel and forming a gate on the gate dielectric. 
     
     
         4 . The method of  claim 1 , wherein forming a gate stack includes:
 forming a gate dielectric on the silicon channel;   forming a floating gate on the gate dielectric;   forming an intergate dielectric on the floating gate; and   forming a control gate on the intergate dielectric.   
     
     
         5 . The method of  claim 1 , wherein forming a gate stack includes forming a multiple layer dielectric on the silicon channel, the multiple layer dielectric having a layer configured to store charge, and forming a gate on the multiple layer dielectric. 
     
     
         6 . The method of  claim 1 , wherein structuring the silicon oxynitride layers includes forming the silicon oxynitride layers as oxygen-rich silicon oxynitride layers to provide compressive strain to the silicon channel. 
     
     
         7 . The method of  claim 1 , wherein forming the silicon oxynitride layers as oxygen-rich silicon oxynitride layers includes forming the silicon oxynitride layers having a ratio of atomic nitrogen to the sum of atomic nitrogen and atomic oxygen less than 0.15. 
     
     
         8 . The method of  claim 1 , wherein structuring the silicon oxynitride layers includes forming the silicon oxynitride layers as nitrogen-rich silicon oxynitride layers to provide tensile strain to the silicon channel. 
     
     
         9 . A method comprising:
 forming a source and a drain of a transistor, the source and drain separated by a silicon channel;   forming a gate stack on the silicon channel;   forming a first spacer adjacent the gate stack and on portion of the drain;   forming a second spacer adjacent the gate stack and on portion of the source; and   forming a capping layer on the gate stack, the first and second spacers, the drain, and the source, the capping layer containing silicon oxynitride structured to control strain in the silicon channel, wherein the silicon oxynitride is formed by high temperature chemical vapor deposition.   
     
     
         10 . The method of  claim 9 , wherein forming a gate stack includes forming a gate dielectric on the silicon channel and forming a gate on the gate dielectric. 
     
     
         11 . The method of  claim 9 , wherein forming a gate stack includes:
 forming a gate dielectric on the silicon channel;   forming a floating gate on the gate dielectric;   forming an intergate dielectric on the floating gate; and   forming a control gate on the intergate dielectric.   
     
     
         12 . The method of  claim 9 , wherein forming a gate stack includes forming a multiple layer dielectric on the silicon channel, the multiple layer dielectric having a layer configured to store charge and forming a gate on the multiple layer dielectric. 
     
     
         13 . The method of  claim 9 , wherein structuring the silicon oxynitride layer includes forming the silicon oxynitride layer as an oxygen-rich silicon oxynitride layer to provide compressive strain to the silicon channel. 
     
     
         14 . The method of  claim 9 , wherein forming the silicon oxynitride layer as an oxygen-rich silicon oxynitride layer includes forming the silicon oxynitride layer having a ratio of atomic nitrogen to the sum of atomic nitrogen and atomic oxygen less than 0.15. 
     
     
         15 . The method of  claim 9 , wherein structuring the silicon oxynitride layer includes forming the silicon oxynitride layer as an nitrogen-rich silicon oxynitride layer to provide tensile strain to the silicon channel. 
     
     
         16 . The method of  claim 9 , wherein forming a first spacer and forming a second spacer includes forming stress-free silicon oxynitride as the first spacer and forming stress-free silicon oxynitride as the second spacer. 
     
     
         17 . The method of  claim 9 , wherein forming a first spacer and forming a second spacer includes forming silicon oxide in tension as the first spacer and forming silicon oxide in tension as the second spacer. 
     
     
         18 . The method of  claim 9 , wherein forming a first spacer includes forming silicon oxynitride as the first spacer and forming a second spacer includes forming a silicon oxynitride as the second spacer, the silicon oxynitride for both the first spacer and the second spacer structured to control strain in the silicon channel in conjunction with the capping layer. 
     
     
         19 . A method comprising:
 forming a source and a drain of a transistor, the source and drain separated by a silicon channel;   forming a gate stack on the silicon channel;   forming a first stress-free spacer adjacent the gate stack and on portion of the drain;   forming a second stress-free spacer adjacent the gate stack and on portion of the source; and   forming a capping layer on the gate stack, the first and second spacers, the drain, and the source, the capping layer containing silicon oxynitride structured to control strain in the silicon channel.   
     
     
         20 . The method of  claim 19 , wherein forming the first stress-free spacer and forming the second stress-free spacer both include forming stress-free silicon oxynitride spacers. 
     
     
         21 . The method of  claim 19 , wherein forming a capping layer on the gate stack includes an oxygen-rich silicon oxynitride layer. 
     
     
         22 . The method of  claim 19 , wherein forming a capping layer on the gate stack includes a nitrogen-rich silicon oxynitride layer.