Shallow trench isolation structure and fabricating method thereof

Abstract

A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

1 . A fabricating method of a shallow trench isolation structure, the fabricating method comprising steps of:
 providing a substrate, wherein a high voltage device area is defined in the substrate;   performing a first etching process to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area;   performing a second etching process to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area; and   filling a dielectric material in the first shallow trench, thereby forming a first shallow trench isolation structure.   
     
     
         2 . The fabricating method according to  claim 1 , wherein a low voltage device area is further defined in the substrate, and a second shallow trench is further formed in the low voltage device area by the second etching process, wherein the first shallow trench is deeper than the second shallow trench. 
     
     
         3 . The fabricating method according to  claim 1 , wherein an inclination angle of a sidewall of the preliminary shallow trench is from 105 to 135 degrees, so that the first shallow trench has a shoulder part with a gentle slope. 
     
     
         4 . The fabricating method according to  claim 3 , wherein after the first shallow trench isolation structure is formed, the fabricating method further comprises steps of:
 performing a pre-clean process to treat the shallow trench isolation structure, so that a top surface of the shallow trench isolation structure is shrunk to a location below the shoulder part; and   forming a high voltage gate dielectric layer on the shallow trench isolation structure and a surface of the substrate.   
     
     
         5 . The fabricating method according to  claim 1 , wherein after the preliminary shallow trench is formed, the fabricating method further comprises a step of forming a spacer on a sidewall of the preliminary shallow trench, wherein the spacer is made of the same material as the dielectric material. 
     
     
         6 . The fabricating method according to  claim 1 , wherein after the preliminary shallow trench is formed and before the second etching process is done, the fabricating method further comprises a step of performing an ion implantation process to dope the high voltage device area of the substrate with a dopant, so that a high voltage well region is formed in the high voltage device area. 
     
     
         7 . The fabricating method according to  claim 1 , wherein the step of filling the dielectric material in the first shallow trench comprises sub-steps of:
 performing a high density plasma chemical vapor deposition process to deposit the dielectric material; and   performing a chemical mechanical polishing process to flatten the dielectric material.   
     
     
         8 . A shallow trench isolation structure, comprising:
 a substrate, wherein a high voltage device area is defined in the substrate;   a first shallow trench formed in the high voltage device area, wherein the first shallow trench has an upper portion and a lower portion, and a sidewall of the upper portion has a shoulder part with a gentle slope; and   a dielectric material layer filled within the first shallow trench to a level near the shoulder part.   
     
     
         9 . The shallow trench isolation structure according to  claim 8 , wherein a low voltage device area is further defined in the substrate, and a second shallow trench is further formed in the low voltage device area by the second etching process, wherein the first shallow trench is deeper than the second shallow trench. 
     
     
         10 . The shallow trench isolation structure according to  claim 8 , wherein an inclination angle of the shoulder part is from 105 to 135 degrees. 
     
     
         11 . The shallow trench isolation structure according to  claim 8 , wherein the substrate is a silicon substrate, and the dielectric material layer is made of silicon oxide. 
     
     
         12 . The shallow trench isolation structure according to  claim 8 , further comprising:
 a high voltage gate dielectric layer formed on a surface of the substrate and in contact with the dielectric material layer; and   a high voltage gate conductor layer formed on the top surfaces of the high voltage gate dielectric layer and the dielectric material layer.   
     
     
         13 . A high voltage metal-oxide-semiconductor field-effect transistor, comprising:
 a substrate;   a channel region formed in the substrate;   at least one shallow trench located at a side of the channel region, wherein the shallow trench has an upper portion and a lower portion, and a sidewall of the upper portion has a shoulder part with a gentle slope; and   a dielectric material layer filled within the first shallow trench to a level near the shoulder part.   
     
     
         14 . The high voltage metal-oxide-semiconductor field-effect transistor according to  claim 13 , wherein an inclination angle of the shoulder part is from 105 to 135 degrees. 
     
     
         15 . The high voltage metal-oxide-semiconductor field-effect transistor according to  claim 13 , wherein the substrate is a silicon substrate, and the dielectric material layer is made of silicon oxide. 
     
     
         16 . The high voltage metal-oxide-semiconductor field-effect transistor according to  claim 13 , further comprising:
 a high voltage gate dielectric layer formed on a surface of the substrate and in contact with the dielectric material layer; and   a high voltage gate conductor layer formed on the top surfaces of the high voltage gate dielectric layer and the dielectric material layer.