Method of manufacturing a printed circuit board having embedded electronic components

Abstract

A method of manufacturing a printed circuit board having embedded electronic components, the method including: mounting a first electronic component on one side of a core sheet and mounting a second electric component on the other side of the core sheet such that the second electronic component overlaps the first electronic component; stacking a first insulation layer on one side of the core sheet such that the first insulation layer covers the first electronic component and stacking a second insulation layer on the other side of the core sheet such that the second insulation layer covers the second electronic component; and forming a circuit pattern on a surface of the first insulation layer or the second insulation layer.

1 . A method of manufacturing a printed circuit board having embedded electronic components, the method comprising:
 mounting a first electronic component on one side of a core sheet and mounting a second electric component on the other side of the core sheet such that the second electronic component overlaps the first electronic component;   stacking a first insulation layer on one side of the core sheet such that the first insulation layer covers the first electronic component and stacking a second insulation layer on the other side of the core sheet such that the second insulation layer covers the second electronic component; and   forming a circuit pattern on a surface of the first insulation layer or the second insulation layer.   
     
     
         2 . The method of  claim 1 , further comprising perforating at least one portion of the core sheet to form at least one core hole, before said stacking the first insulation layer and stacking the second insulation layer, and further comprising forming at least one IVH penetrating the first insulation layer, the second insulation layer, and the core sheet, after said stacking the first insulation layer and stacking the second insulation layer. 
     
     
         3 . The method of  claim 1 , further comprising forming at least one first BVH (blind via hole) in the first insulation layer in correspondence with a position of at least one electrode of the first electronic component and forming at least one second BVH in the second insulation layer in correspondence with a position of at least one electrode of the second electronic component, after said stacking the first insulation layer and stacking the second insulation layer. 
     
     
         4 . The method according to  claim 1 , wherein the core sheet is a metal substrate. 
     
     
         5 . The method according to  claim 1 , wherein the core sheet is a copper clad laminate (CCL). 
     
     
         6 . The method according to  claim 1 , wherein the first electronic component and the second electronic component are identical in size and shape. 
     
     
         7 . The method according to  claim 1 , wherein the first electronic component and the second electronic component are mounted in symmetry with respect to the core sheet. 
     
     
         8 . The method according to  claim 1 , wherein the first electronic component or the second electronic component are mounted on the core sheet by way of chip adhesive applied in-between. 
     
     
         9 . The method according to  claim 1 , wherein the first insulation layer or the second insulation layer is prepreg (PPG) or Ajinomoto build-up film (ABF), and the circuit pattern is formed by stacking a copper foil layer on a surface of the first insulation layer or the second insulation layer. 
     
     
         10 . The method according to  claim 1 , wherein the first insulation layer and the second insulation layer are RCC. 
     
     
         11 . The method according to  claim 2 , wherein the core hole has a cross section greater than that of the IVH such as to allow the IVH to penetrate the core sheet. 
     
     
         12 . The method according to  claim 3 , wherein a plating layer is formed on at least one surface of the at least one first BVH and the at least one second BVH. 
     
     
         13 . The method according to  claim 1 , further comprising stacking an insulation layer and a plating layer on the circuit pattern and forming an outer layer circuit on the plating layer.