System and Method for Video and Audio Encoding on a Single Chip

Abstract

An apparatus is disclosed for performing real time video/audio encoding on a single chip. Within the single chip, a video encoder generates encoded video data from uncompressed video data and an audio encoder generates encoded audio data from uncompressed audio data. A mux processor within the single chip generates an output stream of encoded data from the encoded video data and the encoded audio data.

1 - 9 . (canceled) 
     
     
         10 . A single integrated circuit, comprising:
 multiplexer circuitry configured to receive first video data, first audio data, second video data, and second audio data;   the multiplexer circuitry being configured, in a first mode, to multiplex the first video data, the first audio data, the second video data, and the second audio data into a first multiplexed stream operably coupled via a first output to circuitry external to the single integrated circuit; and   the multiplexer circuitry being configured, in a second mode, to:
 multiplex the first video data and the first audio data into the first multiplexed stream operably coupled via the first output to circuitry external to the single integrated circuit; and 
 multiplex the second video data and the second audio data into a second multiplexed stream operably coupled via a second output to circuitry external to the single integrated circuit. 
   
     
     
         11 . The single integrated circuit of  claim 10 , wherein the first video data, the first audio data, the second video data, and the second audio data are each compressed. 
     
     
         12 . The single integrated circuit of  claim 11 , further comprising encoder circuitry configured to:
 receive first uncompressed video data from a first video source external to the single integrated circuit and compress the first uncompressed video data to produce the first video data;   receive first uncompressed audio data from a first audio source external to the single integrated circuit and compress the first uncompressed audio data to produce the first audio data;   receive second uncompressed video data from a second video source external to the single integrated circuit and compress the second uncompressed video data to produce the second video data; and   receive second uncompressed audio data from a second audio source external to the single integrated circuit and compress the second uncompressed audio data to produce the second audio data.   
     
     
         13 . The single integrated circuit of  claim 12 , wherein the encoder circuitry further comprises:
 a first memory interface that interfaces directly with first storage external to the single integrated circuit, the first uncompressed video data and the first uncompressed audio data being received via the first memory interface; and   a second memory interface that interfaces directly with second storage external to the single integrated circuit, the second uncompressed video data and the second uncompressed audio data being received via the second memory interface.   
     
     
         14 . The single integrated circuit of  claim 12 , further comprising controller circuitry configured to synchronize operation of the multiplexer circuitry and the encoder circuitry. 
     
     
         15 . The single integrated circuit of  claim 14 , further comprising a bus interface that operably couples the controller circuitry and a processor external to the single integrated circuit. 
     
     
         16 . The single integrated circuit of  claim 10 , further comprising circuitry configured to:
 receive the first video data from a first video source external to the single integrated circuit;   receive the first audio data from a first audio source external to the single integrated circuit;   receive the second video data from a second video source external to the single integrated circuit; and   receive the second audio data from a second audio source external to the single integrated circuit.   
     
     
         17 . The single integrated circuit of  claim 10 , wherein each of the first audio data and the second audio data represent at least two audio channels. 
     
     
         18 . The single integrated circuit of  claim 10 , further comprising a corresponding plurality of search processors for performing motion analysis on each of the first video data and the second video data. 
     
     
         19 . The single integrated circuit of  claim 18 , wherein the corresponding plurality of search processors is configured to operate in parallel upon a single macroblock, and each search processor operates at a different one of a plurality of resolutions. 
     
     
         20 . A method, comprising:
 receiving, by multiplexer circuitry in a single integrated circuit, first video data, first audio data, second video data, and second audio data;   responsive to the multiplexer circuitry being in a first mode, multiplexing, by the multiplexer circuitry, the first video data, the first audio data, the second video data, and the second audio data into a first multiplexed stream operably coupled via a first output to circuitry external to the single integrated circuit; and   responsive to the multiplexer circuitry being in a second mode:
 multiplexing, by the multiplexer circuitry, the first video data and the first audio data into the first multiplexed stream operably coupled via the first output to circuitry external to the single integrated circuit; and 
 multiplexing, by the multiplexer circuitry, the second video data and the second audio data into a second multiplexed stream operably coupled via a second output to circuitry external to the single integrated circuit. 
   
     
     
         21 . The method of  claim 20 , wherein the first video data, the first audio data, the second video data, and the second audio data are each compressed. 
     
     
         22 . The method of  claim 21 , further comprising:
 receiving, by encoder circuitry in the single integrated circuit, first uncompressed video data from a first video source external to the single integrated circuit and compress the first uncompressed video data to produce the first video data;   receiving, by the encoder circuitry, first uncompressed audio data from a first audio source external to the single integrated circuit and compress the first uncompressed audio data to produce the first audio data;   receiving, by the encoder circuitry, second uncompressed video data from a second video source external to the single integrated circuit and compress the second uncompressed video data to produce the second video data; and   receiving, by the encoder circuitry, second uncompressed audio data from a second audio source external to the single integrated circuit and compress the second uncompressed audio data to produce the second audio data.   
     
     
         23 . The method of  claim 22 , further comprising:
 receiving, by the encoder circuitry, the first uncompressed video data and the first uncompressed audio data via a first memory interface that interfaces directly with first storage external to the single integrated circuit; and   receiving, by the encoder circuitry, the second uncompressed video data and the second uncompressed audio data via a second memory interface that interfaces directly with second storage external to the single integrated circuit.   
     
     
         24 . The method of  claim 22 , further comprising synchronizing, by controller circuitry in the single integrated circuit, operation of the multiplexer circuitry and the encoder circuitry. 
     
     
         25 . The method of  claim 24 , further comprising operably coupling the controller circuitry and a processor external to the single integrated circuit via a bus interface. 
     
     
         26 . The method of  claim 20 , further comprising:
 receiving, by the single integrated circuit, the first video data from a first video source external to the single integrated circuit;   receiving, by the single integrated circuit, the first audio data from a first audio source external to the single integrated circuit;   receiving, by the single integrated circuit, the second video data from a second video source external to the single integrated circuit; and   receiving, by the single integrated circuit, the second audio data from a second audio source external to the single integrated circuit.   
     
     
         27 . The method of  claim 20 , further comprising performing a motion analysis on each of the first video data and the second video data using a corresponding plurality of search processors in the single integrated circuit. 
     
     
         28 . The method of  claim 27 , wherein the corresponding plurality of search processors is configured to operate in parallel upon a single macroblock, and each search processor operates at a different one of a plurality of resolutions. 
     
     
         29 . A single-chip audio/video encoder device, comprising:
 a first encoder configured to generate first compressed video data and first compressed audio data;   a second encoder configured to generate second compressed video data and second compressed audio data;   a multiplexer configured to receive the first compressed video data and the first compressed audio data from the first encoder and to receive the second compressed video data and the second compressed audio data from the second encoder;   the multiplexer being configured, in a first mode, to multiplex the first compressed video data, the first compressed audio data, the second compressed video data, and the second compressed audio data into a first multiplexed stream operably coupled via a first output to circuitry external to the device; and   the multiplexer being configured, in a second mode, to:
 multiplex the first compressed video data and the first compressed audio data into the first multiplexed stream operably coupled via the first output to circuitry external to the device; and 
 multiplex the second compressed video data and the second compressed audio data into a second multiplexed stream operably coupled via a second output to circuitry external to the device.