Semiconductor memory device having diode cell structure

Abstract

A semiconductor memory device comprises a memory cell, first and second voltage generating circuits generating first and second voltages, and a control circuit. A memory element and a diode included in the memory cell are connected in series between first and second lines. The first voltage has no temperature dependence, and the second voltage has a temperature dependence opposite to that of a forward voltage of the diode. The control circuit detects a resistance state of the memory element in accordance with a change in current flowing in the memory cell in a state where the first/second voltage is applied to the first/second in a read operation of the memory cell.

1 - 14 . (canceled) 
     
     
         15 . A device comprising:
 a memory cell including a resistive memory element and a first diode that are connected in series between a first line and a second line;   a first circuit generating a first voltage to be supplied to the first line;   a second circuit generating a second voltage to be supplied to the second line, and the second circuit including a second diode.   
     
     
         16 . The device as claimed in  claim 15 , wherein the second voltage has temperature dependence opposite to that of a forward voltage of the first diode. 
     
     
         17 . The device as claimed in  claim 16 , wherein the first voltage has no temperature dependence. 
     
     
         18 . The device as claimed in  claim 15 , further comprising:
 a memory array comprising a plurality of the memory cells, a plurality of bit lines including the first line, and a plurality of word lines including the second line, each of the memory cells being associated with one of the bit lines and one of the word lines.   
     
     
         19 . The device as claimed in  claim 18 , wherein, in a read operation of the memory cell, the first voltage is applied to a selected one of the bit lines, the second voltage is applied to a selected one of the word lines, and the ground potential is applied to the other of the bit lines and the other of the word lines. 
     
     
         20 . The device as claimed in  claim 18 , wherein, in a standby state of the memory cell, a ground potential is applied to at least ones of the bit lines and the word lines. 
     
     
         21 . The device as claimed in  claim 15 , wherein the first and second voltages are generated in a read operation of the memory cell. 
     
     
         22 . The device as claimed in  claim 15 , wherein the first voltage is higher than the second voltage. 
     
     
         23 . The device as claimed in  claim 22 , wherein the first voltage is higher than a ground potential and the second voltage is lower than the ground potential. 
     
     
         24 . The device as claimed in  claim 15 , wherein the second circuit further including, a resistor connected to the second diode to generate the second voltage. 
     
     
         25 . The device as claimed in  claim 24 , wherein the second circuit further including,
 a comparator including a first and second input nodes, the first input node receiving a first reference voltage, the second input node each coupled to the resistor and an additional resistor receiving a second reference voltage, and the comparator including an output node.   
     
     
         26 . The device as claimed in  claim 25 , wherein the first input node receives the first voltage. 
     
     
         27 . The device as claimed in  claim 25 , wherein the second circuit further including,
 a ring oscillator circuit coupled to the output node of the comparator and including an output node;   a pumping circuit coupled to the output node of the ring oscillator circuit and outputting the second voltage.   
     
     
         28 . The device as claimed in  claim 15 , further comprising:
 a first reference line supplying a first reference voltage to the first circuit;   a second reference line supplying a second reference voltage to the second circuit.   
     
     
         29 . The device as claimed in  claim 28 , further comprising:
 a connection line connecting an output node of the first circuit to the second circuit to supply the first voltage to the second circuit.   
     
     
         30 . The device as claimed in  claim 29 , wherein the second circuit generates the second voltage in response to the first voltage supplied from the first circuit and the second reference voltage. 
     
     
         31 . The device as claimed in  claim 15 , wherein the first circuit is supplied with a first reference voltage to generate the first voltage, the first voltage relating the first reference voltage. 
     
     
         32 . The device as claimed in  claim 31 , wherein the first reference voltage has no temperature dependence. 
     
     
         33 . The device as claimed in  claim 15 , wherein the second diode of the second circuit has the substantially same in characteristics as the first diode of the memory cell. 
     
     
         34 . The device as claimed in  claim 15 , further comprising:
 a sensing circuit coupled to the second line and sensing a resistance state of the resistive memory element in accordance with a current flowing the second line.   
     
     
         35 . The device as claimed in  claim 15 , wherein the second diode of the second circuit corresponds to the first diode of the memory cell to generate the second voltage. 
     
     
         36 . A method comprising:
 performing a first operation on a memory cell including a resistive memory element and a first diode that are associated with a bit line and a word line;   the performing comprising,
 applying a first voltage to one of the bit line and the word line, 
 generating a second voltage by using a voltage generating circuit including a second diode, and 
 applying the second voltage to the other of the bit line and the word line. 
   
     
     
         37 . The method as claimed in  claim 36 , wherein the first operation is a read operation to read data from the memory cell. 
     
     
         38 . The method as claimed in  claim 36 , wherein the performing further comprises,
 changing the second voltage from a first level to a second level that is higher than the first level when a voltage of a first terminal inserted between the resistive memory element and the first diode changes from a first value to a second value that is lower than the first value,   changing the second voltage from the first level to a third level that is lower than the first level when a voltage value of the first terminal changes from the first value to a third value that is higher than the first value.   
     
     
         39 . The method as claimed in  claim 36 , wherein the second diode of the voltage generating circuit corresponds to the first diode of the memory cell.