Semiconductor device with vertical gate and method of manufacturing the same

Abstract

A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench. First and second source regions are formed in a self-alignment manner by introduction of impurities through the first insulating film.

1 . A method of manufacturing a semiconductor device with vertical gate, comprising the steps of:
 (a) forming a drain region of a first conductivity type on a semiconductor substrate;   (b) forming a first body region of a second conductivity type, which is opposite to the first conductivity type, on the drain region;   (c) forming a trench penetrating the first body region and reaching the drain region;   (d) forming a gate electrode in the trench so as to leave a concave portion on the top of the trench after the step of (c);   (e) forming a first insulating film that is formed in the concave portion and that has a portion in which a thickness increases with an increase in distance from an end of the trench in the first body region on both sides of the trench after the step of (d); and   (f) forming a first source region of the first conductivity type, which is disposed along the trench and which is adjacent to the trench and the top of the gate electrode, by introduction of impurities through the first insulating film after the step of (e).   
     
     
         2 . The method of manufacturing a semiconductor device with vertical gate according to  claim 1 , wherein the step of (d) includes the steps of:
 forming a conductive polysilicon film;   forming a cap insulating film on the conductive polysilicon film; and   forming an interconnection and the gate electrode, which are formed of the conductive polysilicon film covered with the cap insulating film, by processing the cap insulating film and the conductive polysilicon film.   
     
     
         3 . The method of manufacturing a semiconductor device with vertical gate according to  claim 2 , wherein the thickness-increasing portion of the first insulating film has a forward tapered shape with a slope which forms an angle of 30° to 60° with respect to the substrate surface. 
     
     
         4 . The method of manufacturing a semiconductor device with vertical gate according to  claim 3 , wherein in the step of (f), the first insulating film is formed on the entire substrate surface and the introduction of impurities for forming the first source region is carried out by ion implantation. 
     
     
         5 . The method of manufacturing a semiconductor device with vertical gate according to  claim 1 , further comprising the steps of:
 (f1) exposing the substrate surface on both sides of the trench and the side wall of the trench by etching back the first insulating film after the step of (f); and   (f2) forming a second source region of the first conductivity type, which is disposed along the trench, on the top of the first source region by introduction of impurities through the etched-back first insulating film after the step of (f1).   
     
     
         6 . The method of manufacturing a semiconductor device with vertical gate according to  claim 5 , wherein in the step of (f1), the etching-back of the first insulating film is carried out by dry etching or wet etching. 
     
     
         7 . The method of manufacturing a semiconductor device with vertical gate according to  claim 6 , wherein in the step of (f2), the introduction of impurities for forming the second source region is carried out by ion implantation. 
     
     
         8 . The method of manufacturing a semiconductor device with vertical gate according to  claim 1 , further comprising the steps of:
 (g) forming a second insulating film to cover the first insulating film after the step of (f);   (h) forming an embedded insulating film, which is formed of a part of a stacked insulating film including the first insulating film and the second insulating film, in the trench on the gate electrode, and exposing the first body region by etching the stacked insulating film;   (i) forming a second body region of the second conductivity type on the top of the first body region so as to be adjacent to the second source region by introducing impurities into the exposed first body region; and   (j) forming a conductive film which electrically connects the second source region and the second body region.   
     
     
         9 . The method of manufacturing a semiconductor device with vertical gate according to  claim 8 , further comprising a step of planarizing a surface of the stacked insulating film through a CMP between the step of (g) and the step of (h). 
     
     
         10 . The method of manufacturing a semiconductor device with vertical gate according to  claim 9 , wherein in the step of (h), the etching is carried out under such conditions that an etching rate of the stacked insulating film formed in a prearranged region for the second body region is higher than the etching rate of the stacked insulating film formed on the gate electrode. 
     
     
         11 . The method of manufacturing a semiconductor device with vertical gate according to  claim 10 , wherein in the step of (i), the introduction of impurities for forming the second body region is carried out by ion implantation. 
     
     
         12 . The method of manufacturing a semiconductor device with vertical gate according to  claim 11 , further comprising a step of removing a part of the stacked insulating film remaining on the gate electrode through etching, and exposing the second source region from the side wall of the trench between the step of (i) and the step of (j). 
     
     
         13 . The method of manufacturing a semiconductor device with vertical gate according to  claim 12 , wherein the etching in the step of exposing the second source region from the side wall of the trench is carried out under such conditions that the top end portion of the side wall of the trench in the second source region is processed in a curved shape. 
     
     
         14 . The method of manufacturing a semiconductor device with vertical gate according to  claim 1 , further comprising the steps of:
 (e1) isotropically removing a part of the first insulating film and a part of the gate insulating film between the step of (e) and the step of (f); and   (e2) forming a rectangular region on both sides of the top of the trench after the step of (e1).   
     
     
         15 . The method of manufacturing a semiconductor device with vertical gate according to  claim 14 , wherein the step of (f) is a step of forming the first source region on the bottom surface of the rectangular region in a self-alignment manner. 
     
     
         16 . The method of manufacturing a semiconductor device with vertical gate according to  claim 14 , further comprising the steps of:
 (g) forming a second insulating film to cover the first insulating film after the step of (f);   (h) forming an embedded insulating film, which is formed of a part of a stacked insulating film including the first insulating film and the second insulating film, in the trench on the gate electrode, and exposing the first body region by etching the stacked insulating film;   (i) forming a second trench in the exposed first body region and then forming a second body region of the second conductivity type on the bottom of the second trench by introducing impurities into the second trench; and   (j) forming a conductive film which electrically connects the second source region and the second body region to each other.   
     
     
         17 . A semiconductor device with vertical gate comprising:
 a drain region of a first conductivity type that is disposed in a semiconductor substrate;   a first body region of a second conductivity type that is disposed on the drain region and that has a conductivity type opposite to the first conductivity type;   a trench that penetrates the first body region and that reaches the drain region;   a gate electrode that is formed in the trench in a state where a top surface of the gate electrode is located at a position lower than the top end of the trench;   a source region of the first conductivity type that is formed on the surface of the first body region along the trench so as to be adjacent to the trench;   a first insulating film that is formed in the trench on the gate electrode;   a second insulating film that is formed on the first insulating film; and   a conductive film that electrically connects the source region and the body region to each other,   wherein the first insulating film has a concave portion and the second insulating film is disposed to fill the concave portion.   
     
     
         18 . The semiconductor device with vertical gate according to  claim 17 , wherein the source region of the first conductivity type has an impurity region of which a width in the direction perpendicular to a side wall of the trench decreases with an increase in distance in the depth direction of the trench from the surface and of which an impurity concentration increases with a decrease in distance from the top of the side wall of the trench. 
     
     
         19 . The semiconductor device with vertical gate according to  claim 18 , wherein the source region includes a first source region of the first conductivity type and a second source region of the first conductivity type that is formed on the top of the first source region along the trench and that has an impurity concentration higher than that of the first source region. 
     
     
         20 . The semiconductor device with vertical gate according to  claim 18 , wherein a second body region of the second conductivity type that is formed along the source region to be adjacent to the source region and that has an impurity concentration higher than that of the first body region is disposed in the surface portion of the first body region. 
     
     
         21 . The semiconductor device with vertical gate according to  claim 17 , wherein an embedded insulating film including the first insulating film and the second insulating film includes the same type of impurities as in the second source region at least in the bottom portion and includes the same type of impurities as in the second body region at least in the top portion. 
     
     
         22 . The semiconductor device with vertical gate according to  claim 17 , wherein an interface between the source region and the first body region forms a planar shape inclined with respect to the side wall of the trench. 
     
     
         23 . The semiconductor device with vertical gate according to  claim 17 , wherein the second insulating film is disposed to cover the source region. 
     
     
         24 . The semiconductor device with vertical gate according to  claim 17 , wherein a second trench is formed in the surface portion of the first body region so as to be adjacent to the source region,
 wherein the conductive film is disposed in the second trench, and   wherein a second body region of the second conductivity type having an impurity concentration higher than that of the first body region is formed on the bottom of the second trench.   
     
     
         25 . The semiconductor device with vertical gate according to  claim 24 , wherein the second body region is disposed at a position lower than the source region. 
     
     
         26 . The semiconductor device with vertical gate according to  claim 17 , wherein the concave portion is formed by disposing the first insulating film along a side surface of the trench and a top surface of the gate electrode.