Silicon Chip Having Through Via and Method for Making the Same

Abstract

The present invention relates to a silicon chip including a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit.

1 . A silicon chip having a through via, comprising:
 a silicon substrate, having a first surface and a second surface;   a passivation layer, disposed on the first surface of the silicon substrate, wherein the passivation layer has a surface;   at least one electrical device, disposed in the silicon substrate, and exposed to the second surface of the silicon substrate; and   at least one through via, penetrating the silicon substrate and the passivation layer, wherein the through via comprises a barrier layer and a conductor and has a first end and a second end, the first end is exposed to the surface of the passivation layer, and the second end connects the electrical device.   
     
     
         2 . The silicon chip as claimed in  claim 1 , wherein the passivation layer is a material having low dielectric constant, and the dielectric constant of the material is less than  4 . 
     
     
         3 . The silicon chip as claimed in  claim 1 , wherein the material of the passivation layer is polyimide (P 1 ) or benzocyclobutance (BCB). 
     
     
         4 . The silicon chip as claimed in  claim 1 , wherein the electrical device is a complementary metal-oxide-semiconductor (CMOS), 
     
     
         5 . The silicon chip as claimed in  claim 1 , wherein the conductor of the through via is made of copper. 
     
     
         6 . The silicon chip as claimed in  claim 1 , wherein the silicon substrate has a first through hole, the passivation layer has a second through hole, the first through hole and the second through hole have the same diameter, and the through via is formed in the first through hole and the second through hole. 
     
     
         7 . The silicon chip as claimed in  claim 6 , wherein the first through hole and the second through hole connect and align with each other. 
     
     
         8 . The silicon chip as claimed in  claim 1 , further comprising a redistribution layer (RDL) disposed on the surface of the passivation layer, wherein the redistribution layer has at least one electrically connecting area, and the electrically connecting area connects the first end of the through via. 
     
     
         9 . The silicon chip as claimed in  claim 8 , wherein the electrically connecting area of the redistribution layer is larger than a cross-sectional area of the first end of the through via. 
     
     
         10 . The silicon chip as claimed in  claim 8 , wherein the electrically connecting area of the redistribution layer completely covers the first end of the through via. 
     
     
         11 . A silicon chip having a through via, comprising:
 a silicon substrate, having a first surface and a second surface;   a passivation layer, disposed on the first surface of the silicon substrate, wherein the passivation layer has a substantially planar top surface;   at least one electrical device, disposed in the silicon substrate, and exposed to the second surface of the silicon substrate: and   at least one through via, penetrating the silicon substrate and the passivation layer, wherein the through via comprises a barrier layer and a conductor and has a first end and a second end, the first end is coplanar with the top surface of the passivitation layer, and the second end connects the electrical device.   
     
     
         12 . The silicon chip as claimed in  claim 11 , wherein the passivation layer is a material having low dielectric constant, and the dielectric constant of the material is less than 4. 
     
     
         13 . silicon chip as claimed in  claim 11 , wherein the material of the passivation layer is polyimide ( P1 ) or benzocyclobutance (BCB), the electrical device is a complementary metal-oxide-semiconductor (CMOS), and the conductor of the through via is made of copper. 
     
     
         14 . silicon chip as claimed in  claim 11 , wherein the silicon substrate has a first through hole, the passivation layer has a second through hole, the first through hole and the second through hole have the same diameter, and the through via is formed in the first through hole and the second through hole, the first through hole and the second through hole connect and align with each other. 
     
     
         15 . The silicon chip as claimed in  claim 11 , further comprising a redistribution layer (RDL) disposed on the surface of the passivation layer, wherein the redistribution layer has at least one electrically connecting area, and the electrically connecting area connects the first end of the through via. 
     
     
         16 . A silicon chip having a through via, comprising:
 a silicon substrate, having a first surface and a second surface;   a passivation layer, disposed on the first surface of the silicon substrate, wherein the passivation layer has a surface;   at least one through via, penetrating the silicon substrate and the passivation layer, wherein the through via comprises a barrier layer and a conductor and has a first end and a second end, the first end is exposed to the surface of the passivation layer; and   a redistribution layer (RDL) disposed on the surface of the passivation layer and connecting the first end of the through via, wherein the bottom surface of the redistribution layer (RDL) is substantially planar.   
     
     
         17 . The silicon chip as claimed in  claim 16 , wherein the passivation layer is a material having low dielectric constant, and the dielectric constant of the material is less than 4. 
     
     
         18 . The silicon chip as claimed in  claim 16 , wherein the material of the passivation layer is polyimide (PI) or benzocyclobutance (BCB), the electrical device is a complementary metal-oxide-semiconductor (CMOS), and the conductor of the through via is made of copper. 
     
     
         19 . The silicon chip as claimed in  claim 16 , wherein the redistribution layer has at least one electrically connecting area, the electrically connecting area connects the first end of the through via, and the electrically connecting area of the redistribution layer is larger than a cross-sectional area of the first end of the through via. 
     
     
         20 . The silicon chip as claimed in  claim 16 , wherein the redistribution layer has at least one electrically connecting area, the electrically connecting area connects the first end of the through via, and the electrically connecting area of the redistribution layer completely covers the first end of the through via.