Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET

Abstract

A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T inv and V t of the pFET, while scaling Tiny and maintaining Vt for the nFET, resulting in the V t of the pFET becoming closer to the V t of a similarly constructed nFET with scaled T inv values.

1 . A semiconductor structure comprising:
 a semiconductor substrate comprising a semiconductor material;   a p-type field effect transistor (pFET) disposed upon said semiconductor substrate and comprising a semiconductor channel region comprised of SiGe formed upon or within a surface of said semiconductor substrate;   a gate dielectric comprising an oxide layer overlying said semiconductor channel region comprised of SiGe and a high dielectric constant (high-k) dielectric layer overlying said oxide layer; and   a gate electrode overlying said high-k dielectric layer and comprising a lower metal layer abutting said high-k dielectric layer, a scavenging metal layer abutting said lower metal layer, and an upper metal layer abutting said scavenging metal layer, wherein said scavenging metal layer includes a metal (M) for which the Gibbs free energy change of the chemical reaction, in which a silicon atom combines with a metal oxide material including said scavenging metal and oxygen to form said scavenging metal in elemental form and silicon dioxide, is positive; and   an n-type field effect transistor (nFET) also disposed upon said semiconductor substrate and comprising a semiconductor channel region comprised of Si, where the gate electrode of said nFET also comprises said scavenging metal layer.   
     
     
         2 . The semiconductor structure of  claim 1 , where said lower metal layer is comprised of TiN and has a thickness in a range of about 20 Å to about 100 Å and said scavenging metal layer is comprised of Al and has a thickness in a range of about 1 Å to about 20 Å. 
     
     
         3 . The semiconductor structure of  claim 2 , where said upper metal layer is comprised of TiN and has a thickness in a range of about 20 Å to about 100 Å. 
     
     
         4 . The semiconductor structure of  claim 2 , where said semiconductor channel region has a thickness of up to about 100 Å and has a ratio of Ge to Si in a range of about slightly more than zero to about 40%. 
     
     
         5 . The semiconductor structure of  claim 1 , where said lower metal layer and said upper metal layer are comprised of the same material. 
     
     
         6 . The semiconductor structure of  claim 1 , where said scavenging metal layer is comprised of a metal in an elemental form. 
     
     
         7 . The semiconductor structure of  claim 1 , where said lower metal layer and said upper metal layer are comprised of TiN or TiC, or a combination thereof, and wherein said scavenging metal layer includes a metal in an elemental form and is selected from Al, Be, Mg, Ca, Sr, Ba, Sc, Y, La, Zr, Hf, Dy, Lu, Er, Pr, and Ce. 
     
     
         8 . The semiconductor structure of  claim 1 , where said high-k dielectric layer comprises one of HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, an alloy thereof, and non-stoichiometric variants thereof, wherein each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. 
     
     
         9 . The semiconductor structure of  claim 1 , where said gate electrode further comprises a doped polycrystalline semiconductor layer vertically abutting said upper metal layer. 
     
     
         10 . The semiconductor structure of  claim 1 , further comprising a dielectric spacer laterally abutting and surrounding said gate electrode and comprising an oxygen-impermeable material; a source region located in said semiconductor substrate and abutting a peripheral portion of said gate spacer; and a drain region located in said semiconductor substrate and abutting another peripheral portion of said gate spacer. 
     
     
         11 . The semiconductor structure of  claim 1 , where the metal (M) scavenges oxygen from a SiGe interface with said overlying oxide layer resulting in an effective reduction in T inv  and V t  of the pFET. 
     
     
         12 - 21 . (canceled) 
     
     
         22 . A structure, comprising:
 a substrate;   an n-type field effect transistor (nFET) disposed over the substrate, the nFET comprising a Si channel region, a gate dielectric having an oxide layer overlying the channel region, a high-k dielectric layer overlying the oxide layer, and a gate electrode overlying the gate dielectric, said gate electrode comprising a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer, the scavenging metal layer scavenging oxygen from an interface between the Si channel region and the oxide layer; and   a p-type field effect transistor (pFET) disposed over the substrate, the pFET comprising a SiGe channel region, a gate dielectric having an oxide layer overlying the channel region, a high-k dielectric layer overlying the oxide layer, and a gate electrode overlying the gate dielectric, said gate electrode comprising a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer, the scavenging metal layer scavenging oxygen from an interface between the SiGe channel region and the oxide layer.   
     
     
         23 . The structure of  claim 22 , where said lower metal layer and said upper metal layer of each of said nFET and pFET are comprised of TiN or TiC, or a combination thereof, and wherein said scavenging metal layer of each of said nFET and pFET includes a metal in an elemental form and is selected from Al, Be, Mg, Ca, Sr, Ba, Sc, Y, La, Zr, Hf, Dy, Lu, Er, Pr, and Ce. 
     
     
         24 . The structure of  claim 22 , where said lower metal layer of each of said nFET and pFET is comprised of TiN and has a thickness in a range of about 20 Å to about 100 Å, said scavenging metal layer of each of said nFET and pFET is comprised of Al and has a thickness in a range of about 1 Å to about 20 Å, and said upper metal layer of each of said nFET and pFET is comprised of TiN and has a thickness in a range of about 20 Å to about 100 Å. 
     
     
         25 . The structure of  claim 22 , where said SiGe channel region has a thickness of up to about 100 Å and has a ratio of Ge to Si in a range of about slightly more than zero to about 40%.