Replacement Gate ETSOI with Sharp Junction

Abstract

A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.

1 . A transistor structure, comprising:
 a channel disposed between a source and a drain;   a gate conductor disposed over the channel and between the source and the drain; and   a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel; where   the source and the drain are a raised source-drain and a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a source-drain extension region.   
     
     
         2 . The transistor structure of  claim 1 , further comprising a layer of oxide or nitride disposed around the gate conductor and over the source and the drain, and a spacer layer disposed between the oxide layer and the gate dielectric layer, where said spacer layer is disposed but partially over the source and the drain so as not to cover the lower portion of the source and the drain that is adjacent to the channel. 
     
     
         3 . The transistor structure of  claim 1 , where the channel is a portion of an extremely thin silicon on insulator layer, and where the source and the drain are an in-situ doped raised source and drain disposed upon the extremely thin silicon on insulator layer. 
     
     
         4 . The transistor structure of  claim 1 , where the gate dielectric layer is comprised of a high dielectric constant material, and where the gate conductor is comprised of a metal. 
     
     
         5 . The transistor structure of  claim 2 , where the layer of oxide is comprised of SiO 2 , and where the spacer layer is comprised of Si 3 N 4 . 
     
     
         6 . The transistor structure of  claim 1 , where an area of the lower portion of the source and the drain adjacent to the channel that is disposed beneath and in contact with the gate dielectric layer is selected to optimize a tradeoff between capacitance and resistance of the source-drain extension region. 
     
     
         7 . The transistor structure of  claim 1 , fabricated in an extremely thin silicon on insulator wafer. 
     
     
         8 . The transistor structure of  claim 3 , where the source and drain are in-situ doped either p-type or n-type. 
     
     
         9 . The transistor structure of  claim 1 , embodied as a FinFET. 
     
     
         10 .- 19 . (canceled) 
     
     
         20 . An integrated circuit comprising a plurality of transistors, each of said transistors comprising a channel disposed in a layer of silicon and disposed between a raised source-drain structure, a gate conductor disposed over the channel and between the source and the drain and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel; where said raised source-drain structure comprises a source facet and a drain facet that upwardly slope away from channel, where an area of the lower portion of the facet of the source and the facet of the drain that are covered by the gate dielectric layer define a source-drain extension region, and where the area of the lower portion of the facet of the source and the facet of the drain is selected to optimize a tradeoff between capacitance and resistance of the source-drain extension region.