Structures and methods for forming high density trench field effect transistors

Abstract

A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.

1 . A semiconductor structure comprising:
 trenches extending into a semiconductor region, portions of the semiconductor region extending between adjacent trenches forming mesa regions;   a gate electrode in each trench;   well regions of a first conductivity type extending in the semiconductor region between adjacent trenches;   source regions of a second conductivity type in the well regions; and   heavy body regions of the first conductivity type in the well regions, wherein the source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls and to a top surface of the mesa regions.   
     
     
         2 . The semiconductor structure of  claim 1  further comprising:
 a conductor extending into the trenches to contact the source regions along the trench sidewalls. 
 
     
     
         3 . The semiconductor structure of  claim 1  further comprising:
 an interconnect layer extending over the semiconductor region and contacting the heavy body regions along the top surface of the mesa regions. 
 
     
     
         4 . The semiconductor structure of  claim 1  wherein the source regions have portions extending into each trench. 
     
     
         5 . The semiconductor structure of  claim 4  further comprising:
 an interconnect layer extending in each trench to contact the portions of the source regions extending into each trench, the interconnect layer further contacting the heavy body regions along the top surface of the mesa regions. 
 
     
     
         6 . A trench field effect transistor (FET) comprising:
 trenches extending into a semiconductor region;   well regions of a first conductivity type extending in the semiconductor region between adjacent trenches;   heavy body regions of the first conductivity type extending over the well regions and abutting sidewalls of adjacent trenches, wherein a doping concentration of the heavy body regions is greater than a doping concentration of the well regions;   source regions of a second conductivity type abutting the trench sidewalls, the source region being embedded in the well regions below at least a portion of the heavy body regions; and   a gate electrode in each trench, the gate electrode being insulated from the well regions, the heavy body regions, and the source regions by a dielectric.   
     
     
         7 . The trench FET of  claim 6  wherein the source regions overlap the gate electrode along the trench sidewalls. 
     
     
         8 . The trench FET of  claim 6  wherein the heavy body regions include vertically extending portions that are separated from the trenches by the source regions. 
     
     
         9 . The trench FET of  claim 6  further comprising:
 a shield electrode in each trench under the gate electrode; and 
 an inter-electrode dielectric extending between the shield electrode and the gate electrode. 
 
     
     
         10 . The trench FET of  claim 6  further comprising:
 a silicon region in each trench over the gate electrode, wherein the silicon region is isolated from the gate electrode by a dielectric layer, and wherein the silicon region contacts the source regions along the trench sidewalls; and 
 an interconnect layer extending over the semiconductor region and contacting the silicon regions and the heavy body regions. 
 
     
     
         11 . The trench FET of  claim 6  further comprising:
 a source contact in an upper portion of each trench contacting the source regions and the heavy body regions along the trench sidewalls. 
 
     
     
         12 . The trench FET of  claim 6  wherein the source regions have portions extending into each trench, and the portions of the source regions extending into each trench extend over the gate electrode and are insulated from the gate electrode by a dielectric layer. 
     
     
         13 . The trench FET of  claim 12  further comprising:
 an interconnect layer extending in each trench, wherein the interconnect layer contacts the portions of the source regions extending into each trench. 
 
     
     
         14 . A trench field effect transistor (FET) comprising:
 trenches extending into a semiconductor region;   a gate electrode recessed in each trench;   a dielectric extending over the gate electrode;   a source region of a first conductivity type recessed in each trench over the dielectric; and   a source interconnect extending into each trench to contact an upper surface of the source region.   
     
     
         15 . The trench FET of  claim 14  wherein all source contacts are in the trenches. 
     
     
         16 . The trench FET of  claim 14  further comprising:
 a shield electrode in each trench under the gate electrode; and 
 an inter-electrode dielectric extending between the shield electrode and the gate electrode. 
 
     
     
         17 . The trench FET of  claim 14  further comprising:
 well regions of a second conductivity type abutting adjacent trenches, wherein each source region includes portions extending laterally into the well regions; and 
 heavy body regions of the second conductivity type extending directly over the well regions and the laterally extending portions of the source regions, the heavy body regions having a higher doping concentration than the well regions, the laterally extending portions of the source region overlap the gate electrode along trench sidewalls. 
 
     
     
         18 . The trench FET of  claim 14  further comprising:
 well regions of a second conductivity type abutting adjacent trenches; and 
 heavy body regions of the second conductivity type extending over the well regions and abutting upper sidewalls of each trench, wherein a doping concentration of the heavy body regions is greater than a doping concentration of the well regions. 
 
     
     
         19 . The trench FET of  claim 18  wherein the source region is configured so that no portion of the source region abuts any part of the heavy body regions. 
     
     
         20 . The trench FET of  claim 18  wherein the heavy body regions extend along upper surfaces of mesa regions adjacent each trench, and the source interconnect contacts the heavy body regions along the upper surfaces of the mesa regions but is insulated from the heavy body regions along the trench sidewalls.