Memory access unlock

Abstract

In one implementation, a controller is provided such that when an operation is performed at a first memory location, the controller unlocks access to a second memory location.

1 . An apparatus, comprising:
 a memory having a first and second memory location, the first memory location being in a first memory map space and the second memory location being in a second memory map space; and   a controller operatively coupled to the memory to unlock access to the second memory location based on an operation to the first memory location.   
     
     
         2 . The apparatus of  claim 1 , wherein the controller is further to:
 automatically lock access to the second memory location a predetermined period of time after access has been unlocked, wherein the predetermined period of time is one of a processor-relative time period, an absolute time period, and a work time period.   
     
     
         3 . The apparatus of  claim 1 , where the controller is further to:
 automatically lock access to the second memory location after completion of an operation to the second memory location.   
     
     
         4 . The apparatus of  claim 1 , further comprising:
 a third memory location, wherein
 the controller unlocks access to the second memory location for a write operation based on the operation to the first memory location; and 
 the controller unlocks access to the second memory location for read operation based on an operation to the third memory location. 
   
     
     
         5 . The apparatus of  claim 1 , wherein the controller is to permit a predetermined number of operations to the second memory location after the access to the second memory location is unlocked. 
     
     
         6 . An apparatus, comprising:
 a controller to unlock access to a first memory location in a first memory map space based on an operation to a second memory location in a second memory map space.   
     
     
         7 . The apparatus of  claim 6 , further comprising:
 a clock; and   a counter to count clock cycles;   wherein the controller is to automatically lock access to the first memory location after a predetermined number of counted clock cycles.   
     
     
         8 . The apparatus of  claim 6 , wherein the operation is a write operation to the second memory location. 
     
     
         9 . The apparatus of  claim 6 , wherein the operation is a read operation to the second memory location. 
     
     
         10 . The apparatus of  claim 6 , wherein the write operation includes writing a predetermined value to the second memory location. 
     
     
         11 . The apparatus of  claim 6 , the apparatus further including:
 a third memory location, wherein
 if the first memory location is an odd number address, the controller is to unlock access to the first memory location based on an operation to the second memory location; and 
 if the first memory location is an even number address, the controller is to unlock access to the first memory location based on an operation to the third memory location. 
   
     
     
         12 . The apparatus of  claim 6 , the controller to:
 automatically lock access to the unlocked first memory location.   
     
     
         13 . A method, comprising:
 receiving a signal indicating an operation has been performed at a control register; and   unlocking access to a memory region based on the operation that has been performed at the control register.   
     
     
         14 . The method of  claim 13 , further comprising:
 automatically locking access to the memory region after one of an operation to the memory region and a predetermined time period after unlocking access to the memory region.   
     
     
         15 . The method of  claim 13 , further comprising:
 unlocking access to the second memory location for a write operation based on the operation to the first memory location; and   the controller unlocks access to the second memory location for read operation based on an operation to the third memory location.