Method and apparatus for high speed cache flushing in a non-volatile memory

Abstract

An invention is provided for performing flush cache in a non-volatile memory. The invention includes maintaining a plurality of free memory blocks within a non-volatile memory. When a flush cache command is issued, a flush cache map is examined to obtain a memory address of a memory block in the plurality of free memory blocks within the non-volatile memory. The flush cache map includes a plurality of entries, each entry indicating a memory block of the plurality of free memory blocks. Then, a cache block is written to a memory block at the obtained memory address within the non-volatile memory. In this manner, when a flush cache command is received, the flush cache map allows cache blocks to be written to free memory blocks in the non-volatile memory without requiring a non-volatile memory search for free blocks or requiring erasing of memory blocks storing old data.

1 . A method for performing a cache flush in a non-volatile memory, comprising the operations of:
 maintaining a plurality of free memory blocks within a non-volatile memory until a flush cache command is received;   examining a flush cache map in response to the flush cache command to obtain a memory address of a memory block of the plurality of free memory blocks within the non-volatile memory, wherein the flush cache map includes a plurality of entries, each entry indicating a memory block of the plurality of free memory blocks;   writing a cache block to a memory block at the obtained memory address within the non-volatile memory, wherein the plurality of free memory blocks comprises a predetermined number of free memory blocks, and wherein the predetermined number is based on a predetermined number of cache blocks.   
     
     
         2 . The method as recited in  claim 1 , wherein each entry of the plurality of entries indicates a different free memory block of the plurality of free memory blocks in the non-volatile memory. 
     
     
         3 . The method as recited in  claim 1 , wherein the plurality of free memory blocks comprises a predetermined number of free memory blocks, and wherein the predetermined number is based on a predetermined number of cache blocks. 
     
     
         4 . The method as recited in  claim 1 , wherein the plurality of entries in the flush cache map is examined sequentially to obtain addresses of free memory blocks in which to store cache blocks. 
     
     
         5 . The method as recited in  claim 1 , wherein the flush cache map further includes an entry indicating a free memory block in which to store a block table, wherein the block table includes a plurality of entries mapping a physical block address of the non-volatile memory to a logical block address. 
     
     
         6 . A method for performing a cache flush in a non-volatile memory, comprising the operations of:
 maintaining a plurality of free memory blocks within a non-volatile memory;   examining a flush cache map to obtain a memory address of a memory block of the plurality of free memory blocks within the non-volatile memory, wherein the flush cache map includes a plurality of entries, each entry indicating a memory block of the plurality of free memory blocks;   writing a cache block to a free memory block at the obtained memory address within the non-volatile memory; and   examining the flush cache map to obtain an additional memory address of a memory block of the plurality of free memory blocks within the non-volatile memory, wherein a block table is written to a free memory block at the obtained additional memory address within the non-volatile memory, wherein the plurality of free memory blocks comprises a predetermined number of free memory blocks, and wherein the predetermined number is based on a predetermined number of cache blocks.   
     
     
         7 . The method as recited in  claim 6 , wherein the block table includes a plurality of entries mapping a physical block address of the non-volatile memory to a logical block address. 
     
     
         8 . The method as recited in  claim 6 , wherein each pointer of the plurality of entries indicates a different free memory block of the plurality of free memory blocks in the non-volatile memory. 
     
     
         9 . The method as recited in  claim 6 , wherein the plurality of free memory blocks comprises a predetermined number of free memory blocks, and wherein the predetermined number is based on a predetermined number of cache blocks. 
     
     
         10 . The method as recited in  claim 6 , wherein the plurality of entries in the flush cache map is examined sequentially to obtain addresses of free memory blocks in which to store cache blocks. 
     
     
         11 . The method as recited in  claim 6 , wherein the flush cache map is examined in response to a flush cache command. 
     
     
         12 . The method as recited in  claim 6 , wherein the block table includes wear level data for memory blocks in the non-volatile memory. 
     
     
         13 . A flush cache map for high speed cache flush in a non-volatile memory, comprising:
 a predetermined number of entries, wherein each entry indicates a free memory block within a non-volatile memory, and wherein each free memory block is maintained free of data during operation of the non-volatile memory; and   an additional entry indicating an additional free memory block within the non-volatile memory, wherein a block table is written to the additional free memory block within the non-volatile memory.   
     
     
         14 . The flush cache map as recited in  claim 13 , wherein the predetermined number is based on a predetermined number of cache blocks. 
     
     
         15 . The flush cache map as recited in  claim 13 , wherein the predetermined number is further based on a predetermined number of cache blocks plus one. 
     
     
         16 . The flush cache map as recited in  claim 13 , wherein each entry of the plurality of pointers indicates a different free memory block in the non-volatile memory. 
     
     
         17 . The flush cache map as recited in  claim 13 , wherein each entry is generated during system power-up.