Direct digital synthesizer for reference frequency generation

Abstract

A direct digital frequency synthesizer includes a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The divider receives an input clock having an input pulse frequency and outputs some integer fraction of those pulses at an instantaneous frequency that is some integer fraction (1/P) of the input frequency. The divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the oscillator. The oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the divider to change divider ratios in response to receiving an overflow signal. The oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator.

1 . A method for providing an output signal with an adjusted frequency, the method comprising:
 receiving a clock reference signal at a first input frequency;   dividing the input frequency to generate an intermediate signal with an adjusted frequency, wherein the intermediate signal comprises a plurality of pulses;   providing a phase value from an oscillator in response to receiving an accumulator increment value;   clocking a latch circuit using the intermediate signal with the adjusted frequency;   outputting, from the numerically controlled oscillator, a delay value and an overflow value;   selecting between at least a first divider ratio and a second divider ratio based on the overflow value; and   in response to receiving at least the overflow value and the delay value, calculating a delay time for application to each pulse in the intermediate signal to provide an output signal with a final adjusted frequency.