US2013020687A1PendingUtilityA1
Power module package and method for manufacturing the same
Est. expiryJul 20, 2031(~5 yrs left)· nominal 20-yr term from priority
H10W 90/756H10W 90/753H10W 90/736H10W 74/00H10W 72/884H10W 90/811H10W 90/00H10W 76/47H10W 74/111H10W 74/016H10W 70/458H10W 70/442H10W 40/778H10W 95/00H10W 72/851
47
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead frames.
Claims
exact text as granted — not AI-modified1 . A power module package, comprising:
first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead fumes.
2 . The power module package as set forth in claim 1 , wherein the ceramic coating layer is formed by a sol-gel method.
3 . The power module package as set forth in claim 1 , wherein the semiconductor device includes a power device and a control device, and
when the ceramic coating layers are formed on both of the first and second lead frames, the second surface of the first lead frame is mounted with the power device and the second surface of the second lead frame is mounted with the control device.
4 . The power module package as set forth in claim 1 , wherein the semiconductor device includes a power device and a control device, and
when the ceramic coating layer is formed on the first lead frame, the second surface of the first lead frame is mounted with the power device and the second surface of the second lead frame is mounted with the control device.
5 . The power module package as set forth in claim 1 , further comprising a thermal diffusion layer made of a metal material formed on a lower surface of the ceramic coating layer over the first and second lead frames.
6 . The power module package as set forth in claim 1 , wherein both or one of both of the first and second lead frames has a down-set structure.
7 . The power module package as set forth in claim 1 , further comprising:
a wire electrically connecting between the semiconductor devices or between the semiconductor device and the lead frame; and a molding formed on upper portions of the first and second lead frames, between the first lead frame and the second lead frame, and on a portion of lower portions of the first and second lead frames.
8 . The power module package as set forth in claim 7 , wherein the molding is formed in a form that exposes the ceramic coating layer formed on the lower portions of the first and second lead frames.
9 . A method for manufacturing a power module package, comprising:
preparing first and second lead frames disposed to face each other; forming ceramic coating layers on a portion of a first surface of both or one of both of the first and second lead frames; and mounting semiconductor devices on second surfaces of the first and second lead frames.
10 . The method as set forth in claim 9 , wherein at the forming of the ceramic coating layer, the ceramic coating layer is formed by a sol-gel method.
11 . The method as set forth in claim 9 , wherein the semiconductor device includes a power device and a control device, and
when the ceramic coating layers are formed on both of the first and second lead frames, at the mounting of the semiconductor device, the second surface of the first lead frame is mounted with the power device and the second surface of the second lead frame is mounted with the control device.
12 . The method as set forth in claim 9 , wherein the semiconductor device includes a power device and a control device, and
when the ceramic coating layer is formed on the first lead frame, at the mounting of the semiconductor device, the second surface of the first lead frame is mounted with the power device and the second surface of the second lead frame is mounted with the control device.
13 . The method as set forth in claim 9 , further comprising:
after the mounting of the semiconductor device, forming a wire electrically connecting between the semiconductor devices or between the semiconductor device and the lead frame; and forming a molding so as to cover an upper portion of the semiconductor device mounted between the first and second lead frames, on a portion of lower portions of the first and second lead frames, and on upper portions of the first lead frame and the second lead frame.
14 . The method as set forth in claim 13 , further comprising, prior to forming of the molding, forming a thermal diffusion layer made of a metal material on a lower surface of the ceramic coating layer over the first and second lead frames.
15 . The method as set forth in claim 13 , further comprising, after the forming of the molding, forming forms of the first and second lead frames.
16 . The method as set forth in claim 13 , further comprising, prior to the forming of the molding, forming a form having a down-set structure on both or one of both of the first and second lead frames.
17 . The method as set forth in claim 13 , wherein at the forming of the molding, the molding is formed in a form that exposes the ceramic coating layers formed on the lower portions of the first and second lead frames.Join the waitlist — get patent alerts
Track US2013020687A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.