Thermoelectric devices, systems and methods

Abstract

A method for forming a thermoelectric element for use in a thermoelectric device comprises forming a mask adjacent to a substrate. The mask can include three-dimensional structures phase-separated in a polymer matrix. The three-dimensional structures can be removed to provide a plurality of holes in the polymer matrix. The plurality of holes can expose portions of the substrate. A layer of a metallic material can be deposited adjacent to the mask and exposed portions of the substrate. The mask can then be removed. The metallic material is then exposed to an oxidizing agent and an etchant to form holes or wires in the substrate.

1 . A method for forming a thermoelectric device, comprising:
 (a) forming a mask adjacent to a substrate, the mask having three-dimensional structures phase-separated in a polymer matrix;   (b) removing the three-dimensional structures or the polymer matrix to expose portions of said substrate;   (c) depositing an etching layer adjacent to exposed portions of said substrate; and   (d) catalytically etching the substrate with an oxidizing agent and an etchant.   
     
     
         2 . The method of  claim 1 , wherein, in (b), said three-dimensional structures are selectively removed in relation to the polymer matrix. 
     
     
         3 . The method of  claim 2 , wherein, in (d), said catalytically etching the substrate forms holes in the substrate. 
     
     
         4 . The method of  claim 1 , wherein, between (b) and (c), an etch block layer is deposited on exposed portions of said substrate, and said mask is removed. 
     
     
         5 . The method of  claim 4 , wherein said etch block layer comprises a material that reduces an etch rate of portions of said substrate that are adjacent to said etch block layer. 
     
     
         6 . The method of  claim 4 , wherein, in (d), said catalytically etching the substrate forms holes in the substrate. 
     
     
         7 . The method of  claim 1 , wherein the etching layer comprises gold, silver, platinum, chromium, molybdenum, tungsten, palladium, other noble metals, and/or combinations thereof. 
     
     
         8 . The method of  claim 1 , wherein the three-dimensional structures are formed of a polymeric material. 
     
     
         9 . The method of  claim 8 , wherein the three-dimensional structures are formed of a block copolymer. 
     
     
         10 . The method of  claim 1 , wherein, after (c), said mask is removed to expose portions of said substrate. 
     
     
         11 . The method of  claim 1 , wherein said substrate comprises one or more semiconductors. 
     
     
         12 . A method for forming a thermoelectric device, comprising:
 providing a polymer matrix adjacent to a substrate, said polymer matrix having three-dimensional structures phase-separated therein;   selectively removing one of the three-dimensional structures or the polymer matrix in relation to the other to provide a mask that includes (i) a plurality of holes in the polymer matrix or (ii) said three-dimensional structures disposed adjacent to the substrate, wherein said mask exposes portions of said substrate, and wherein said mask has a pattern that is characterized by the distribution of said plurality of holes or three-dimensional structures; and   catalytically transferring said pattern to said substrate.   
     
     
         13 . The method of  claim 12 , wherein said pattern includes said plurality of holes, and said catalytically transferring said pattern to said substrate generates holes in said substrate. 
     
     
         14 . The method of  claim 12 , wherein said pattern includes said three-dimensional structures, and said catalytically transferring said pattern to said substrate generates wires in said substrate. 
     
     
         15 . The method of  claim 12 , wherein said catalytically transferring said pattern to said substrate comprises:
 depositing a layer of an etching material adjacent to exposed portions of said substrate; and   catalytically etching the substrate with an oxidizing agent and an etchant with the aid of said etching material.   
     
     
         16 . The method of  claim 15 , further comprising depositing a layer of an etch block material adjacent to said substrate prior to depositing said layer of the etching material. 
     
     
         17 . The method of  claim 16 , wherein an etch rate of portions of said substrate adjacent to said etching material is greater than an etch rate of portions of said substrate adjacent to said etch block material. 
     
     
         18 . The method of  claim 16 , wherein said catalytically etching the substrate forms holes in the substrate. 
     
     
         19 . The method of  claim 15 , wherein said catalytically etching the substrate forms holes in the substrate. 
     
     
         20 . The method of  claim 15 , wherein the etching material comprises gold, silver, platinum, chromium, molybdenum, tungsten, palladium, other noble metals, and/or combinations thereof. 
     
     
         21 . The method of  claim 12 , wherein the three-dimensional structures are formed of a polymeric material. 
     
     
         22 . The method of  claim 21 , wherein the three-dimensional structures are formed of a block copolymer. 
     
     
         23 . The method of  claim 12 , wherein catalytically transferring said pattern to said substrate comprises removing said mask. 
     
     
         24 . The method of  claim 12 , wherein said substrate comprises one or more semiconductors. 
     
     
         25 . A method for forming a thermoelectric device, comprising:
 providing a pattern of holes or wires adjacent to a substrate; and   catalytically etching said substrate to transfer said pattern to said substrate to form wires or holes in said substrate,   wherein each of said wires or holes has an aspect ratio of at least about 20:1, and   wherein an etch rate of said substrate is at least about 0.1 nanometers (nm) per second at 25° C.   
     
     
         26 . The method of  claim 25 , wherein said substrate comprises one or more semiconductors. 
     
     
         27 . The method of  claim 25 , wherein said etch rate is at least about 1 nm per second at 25° C. 
     
     
         28 . The method of  claim 25 , wherein said etch rate is at least about 10 nm per second at 25° C. 
     
     
         29 . A method for forming a thermoelectric device, comprising:
 (a) providing, adjacent to a substrate, a polymer matrix having three-dimensional structures distributed therein;   (b) selectively removing one of the polymer matrix or the three-dimensional structures in relation to the other, thereby providing a mask having a pattern of holes or said three-dimensional structures disposed adjacent to the substrate;   (c) depositing a layer of an etching material adjacent to the substrate; and   (d) catalytically etching the substrate with the aid of said etching material.   
     
     
         30 . The method of  claim 29 , wherein said substrate comprises one or more semiconductors. 
     
     
         31 . The method of  claim 29 , wherein, in (a), said three-dimensional structures are phase-separated in said polymer matrix. 
     
     
         32 . The method of  claim 29 , wherein, in (b), said polymer matrix is selectively removed in relation to said three-dimensional structures. 
     
     
         33 . The method of  claim 29 , wherein catalytically etching the substrate in (d) forms holes in the substrate. 
     
     
         34 . The method of  claim 29 , wherein, prior to (c), a second layer of an etch block material is deposited adjacent to said substrate. 
     
     
         35 . The method of  claim 34 , wherein, in (b), the three-dimensional structures are selectively removed in relation to the polymer matrix to provide a pattern of holes, and wherein said second layer is deposited in an individual hole of said holes. 
     
     
         36 . The method of  claim 34 , wherein, in (d), said catalytically etching the substrate forms holes in the substrate. 
     
     
         37 . The method of  claim 29 , wherein the layer of the etching material comprises gold, silver, platinum, chromium, molybdenum, tungsten, palladium, other noble metals, and/or combinations thereof. 
     
     
         38 . The method of  claim 29 , wherein the three-dimensional structures are formed of a polymeric material. 
     
     
         39 . The method of  claim 38 , wherein the three-dimensional structures are formed of a block copolymer. 
     
     
         40 . A thermoelectric device, comprising a first thermoelectric element electrically coupled to a second thermoelectric element, each of said first and second thermoelectric elements having a semiconductor substrate that is doped p-type or n-type, wherein the semiconductor substrate of each of said first and second thermoelectric elements comprises a pattern of holes, an individual hole of said pattern having an aspect ratio of at least about 20:1. 
     
     
         41 . The device of  claim 40 , wherein said holes are oriented anti-parallel in relation to an electrode coupled to said substrate. 
     
     
         42 . The device of  claim 41 , wherein said holes are oriented perpendicularly in relation to said electrode. 
     
     
         43 . The device of  claim 40 , wherein said holes of said pattern are monodisperse. 
     
     
         44 . The device of  claim 40 , wherein said individual hole has a surface with a metal content of at least about 0.000001% as measured by x-ray photoelectron spectroscopy (XPS). 
     
     
         45 . The device of  claim 40 , wherein said individual hole has a surface roughness between about 0.5 nanometers (nm) and 50 nm as measured by transmission electron microscopy (TEM). 
     
     
         46 . The device of  claim 45 , wherein said surface roughness is between about 1 nm and 20 nm as measured by TEM. 
     
     
         47 . The device of  claim 46 , wherein said surface roughness is between about 1 nm and 10 nm as measured by TEM. 
     
     
         48 . The device of  claim 40 , wherein exposed surfaces of said hole comprise an oxide of said semiconductor substrate. 
     
     
         49 . The device of  claim 48 , wherein said oxide is a native oxide. 
     
     
         50 . The device of  claim 40 , wherein said semiconductor substrate comprises silicon. 
     
     
         51 . The device of  claim 40 , wherein said aspect ratio is at least about 50:1. 
     
     
         52 . The device of  claim 40 , wherein said aspect ratio is at least about 100:1. 
     
     
         53 . The device of  claim 40 , wherein said aspect ratio is at least about 1,000:1. 
     
     
         54 . The device of  claim 40 , wherein said aspect ratio is at least about 5,000:1. 
     
     
         55 . The device of  claim 40 , wherein said aspect ratio is at least about 10,000:1. 
     
     
         56 . The device of  claim 40 , wherein said aspect ratio is at least about 100,000:1. 
     
     
         57 . The device of  claim 40 , wherein said pattern of holes has a pitch less than about 1000 nanometers. 
     
     
         58 . The device of  claim 57 , wherein said pattern of holes has a pitch less than about 100 nanometers. 
     
     
         59 . The device of  claim 58 , wherein said pattern of holes has a pitch less than about 20 nanometers. 
     
     
         60 . The device of  claim 40 , wherein an individual hole is filled with a dielectric material. 
     
     
         61 . The device of  claim 40 , wherein said first and second thermoelectric elements are oppositely doped n-type or p-type. 
     
     
         62 . A thermoelectric device, comprising:
 a first thermoelectric element formed of an n-type or p-type semiconductor substrate; and   a second thermoelectric element electrically coupled to said first thermoelectric element and formed of an n-type or p-type semiconductor substrate,   wherein the semiconductor substrate of each of said first and second thermoelectric elements comprises a pattern of holes or wires, an individual hole or wire of said pattern having an aspect ratio of at least about 20:1 and a surface roughness between about 0.5 nanometers (nm) and 50 nm as measured by transmission electron microscopy (TEM).   
     
     
         63 . The device of  claim 62 , wherein said pattern comprises holes or wires that are monodisperse. 
     
     
         64 . The device of  claim 62 , wherein an individual hole or wire has a surface with a metal content of at least about 0.000001% as measured by x-ray photoelectron spectroscopy (XPS). 
     
     
         65 . The device of  claim 62 , wherein said surface roughness is between about 1 nm and 20 nm as measured by TEM. 
     
     
         66 . The device of  claim 62 , wherein said surface roughness is between about 1 nm and 10 nm as measured by TEM. 
     
     
         67 . The device of  claim 62 , wherein exposed surfaces of said semiconductor substrate comprise an oxide of said semiconductor substrate. 
     
     
         68 . The device of  claim 67 , wherein said oxide is a native oxide. 
     
     
         69 . The device of  claim 62 , wherein said semiconductor substrate comprises silicon. 
     
     
         70 . The device of  claim 62 , wherein said aspect ratio is at least about 50:1. 
     
     
         71 . The device of  claim 62 , wherein said aspect ratio is at least about 100:1. 
     
     
         72 . The device of  claim 62 , wherein said aspect ratio is at least about 1,000:1. 
     
     
         73 . The device of  claim 62 , wherein said aspect ratio is at least about 5,000:1. 
     
     
         74 . The device of  claim 62 , wherein said aspect ratio is at least about 10,000:1. 
     
     
         75 . The device of  claim 62 , wherein said aspect ratio is at least about 100,000:1. 
     
     
         76 . The device of  claim 62 , wherein said pattern of holes or wires has a pitch less than about 1000 nanometers. 
     
     
         77 . The device of  claim 76 , wherein said pattern of holes or wires has a pitch less than about 100 nanometers. 
     
     
         78 . The device of  claim 77 , wherein said pattern of holes or wires has a pitch less than about 20 nanometers. 
     
     
         79 . The device of  claim 62 , wherein at least one of said first and second thermoelectric elements has a pattern of holes. 
     
     
         80 . The device of  claim 62 , wherein said first and second thermoelectric elements each has a pattern of holes. 
     
     
         81 . The device of  claim 79  or  80 , wherein an individual hole of said pattern of holes is filled with a dielectric material. 
     
     
         82 . The device of  claim 62 , wherein at least one of said first and second thermoelectric elements has a pattern of wires. 
     
     
         83 . The device of  claim 62 , wherein said first and second thermoelectric elements each has a pattern of wires. 
     
     
         84 . The device of  claim 82  or  83 , wherein individual wires of said pattern of wires are laterally separated by a dielectric material. 
     
     
         85 . The device of  claim 62 , wherein said first and second thermoelectric elements are oppositely doped n-type or p-type. 
     
     
         86 . A thermoelectric element, comprising a semiconductor substrate that is doped p-type or n-type and having a pattern of holes or wires, an individual hole or wire of said pattern having an aspect ratio of at least about 20:1 and a surface roughness between about 0.5 nanometers (nm) and 50 nm as measured by transmission electron microscopy (TEM). 
     
     
         87 . The thermoelectric element of  claim 86 , wherein said pattern comprises holes or wires that are monodisperse. 
     
     
         88 . The thermoelectric element of  claim 86 , wherein an individual hole or wire has a surface with a metal content of at least about 0.001% as measured by x-ray photoelectron spectroscopy (XPS). 
     
     
         89 . The thermoelectric element of  claim 86 , wherein said surface roughness is between about 1 nm and 20 nm as measured by TEM. 
     
     
         90 . The thermoelectric element of  claim 86 , wherein said surface roughness is between about 1 nm and 10 nm as measured by TEM. 
     
     
         91 . The thermoelectric element of  claim 86 , wherein exposed surfaces of said semiconductor substrate comprise an oxide of said semiconductor substrate. 
     
     
         92 . The thermoelectric element of  claim 91 , wherein said oxide is a native oxide. 
     
     
         93 . The thermoelectric element of  claim 86 , wherein said semiconductor substrate comprises silicon. 
     
     
         94 . The thermoelectric element of  claim 86 , wherein said aspect ratio is at least about 50:1. 
     
     
         95 . The thermoelectric element of  claim 86 , wherein said aspect ratio is at least about 100:1. 
     
     
         96 . The thermoelectric element of  claim 86 , wherein said aspect ratio is at least about 1,000:1. 
     
     
         97 . The thermoelectric element of  claim 86 , wherein said aspect ratio is at least about 5,000:1. 
     
     
         98 . The thermoelectric element of  claim 86 , wherein said aspect ratio is at least about 10,000:1. 
     
     
         99 . The thermoelectric element of  claim 86 , wherein said aspect ratio is at least about 100,000:1. 
     
     
         100 . The thermoelectric element of  claim 86 , wherein said pattern of holes or wires has a pitch less than about 1000 nanometers. 
     
     
         101 . The thermoelectric element of  claim 100 , wherein said pattern of holes or wires has a pitch less than about 100 nanometers. 
     
     
         102 . The thermoelectric element of  claim 101 , wherein said pattern of holes or wires has a pitch less than about 20 nanometers. 
     
     
         103 . The thermoelectric element of  claim 86 , wherein said thermoelectric element has a pattern of holes. 
     
     
         104 . The thermoelectric element of  claim 103 , wherein an individual hole of said pattern of holes is filled with a dielectric material. 
     
     
         105 . The thermoelectric element of  claim 86 , wherein said thermoelectric element has a pattern of wires. 
     
     
         106 . The thermoelectric element of  claim 105 , wherein individual wires of said pattern of wires are laterally separated by a dielectric material.