US2013015912A1PendingUtilityA1

Soi cmos structure having programmable floating backplate

Assignee: IBMPriority: Nov 16, 2009Filed: Sep 12, 2012Published: Jan 17, 2013
Est. expiryNov 16, 2029(~3.3 yrs left)· nominal 20-yr term from priority
H10D 86/201H10D 30/711H10D 86/00H10D 86/01
48
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Claims

Abstract

SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

Claims

exact text as granted — not AI-modified
1 . A method of operating at least one field effect transistor, said method comprising:
 providing a semiconductor structure including a buried floating conductive material portion embedded in a substrate, a first buried insulator layer contacting a bottom surface of said buried floating conductive material portion, a second buried insulator layer contacting a top surface of said buried floating conductive material portion, a top semiconductor layer including source and drain regions of at least one field effect transistor, and an injection means for injecting electrons through said second buried insulator layer; and   injecting electrons from said injection means though said second buried insulator layer into said buried floating conductive material portion, wherein electrons accumulated in said buried floating conductive material portion alter a threshold voltage of said at least one field effect transistor.   
     
     
         2 . The method of  claim 1 , wherein said injection means includes:
 a p-type injector field effect transistor, wherein source and drain regions of said p-type field effect transistor are located in said top semiconductor layer; and   a switchable voltage supply system configured to provide a voltage differential across said drain region and said source region of said p-type injector field effect transistor, wherein said p-type injector field effect transistor is configured to generate hot electrons having sufficient energy to pass though said second buried insulator layer and to flow into said buried floating conductive material portion.   
     
     
         3 . The method of  claim 2 , further comprising applying a positive voltage to said source and drain regions of said p-type injector field effect transistor, whereby electrons are removed by tunneling from said buried floating conductive material portion through said second buried insulator layer into said p-type injector field effect transistor. 
     
     
         4 . The method of  claim 2 , further comprising applying a positive voltage to an n-doped semiconductor region located in said top semiconductor layer, whereby electrons are removed by tunneling from said buried floating conductive material portion through said second buried insulator layer into said n-doped semiconductor region. 
     
     
         5 . The method of  claim 1 , wherein said injection means includes:
 an n-doped semiconductor region; and   a switchable voltage supply system configured to provide at least one voltage to said n-doped semiconductor region, wherein said at least one voltage has a magnitude that is high enough to induce tunneling of electrons though said second buried insulator layer into or out of said buried floating conductive material portion.   
     
     
         6 . The method of  claim 1 , further comprising removing electrons from said buried floating conductive material portion by inducing tunneling of electrons through said second buried insulator layer into a structure located in said top semiconductor layer. 
     
     
         7 . The method of  claim 6 , wherein said removing of electrons is effected by applying a positive voltage to an n-doped semiconductor region located in said top semiconductor layer.

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