Array substrate and method for manufacturing the array substrate

Abstract

An array substrate including: a gate electrode and a gate insulation layer disposed on a base substrate, the gate insulation layer having a first thickness in a first region and a second thickness in a second region, the first thickness being greater than the second thickness; a semiconductor pattern disposed on the gate insulation layer in the first region, an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer; an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern opposite to a channel portion being aligned with the end portion of the semiconductor pattern; and source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes spaced apart from each other and including first and second thin-film transistor patterns.

1 . An array substrate comprising:
 a gate electrode disposed on a base substrate;   a gate insulation layer disposed on the base substrate on which the gate electrode is disposed, the gate insulation layer having a first thickness in a first region and a second thickness in a second region, the first thickness being greater than the second thickness;   a semiconductor pattern disposed on the gate insulation layer in the first region, an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer;   an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern, which is disposed substantially opposite to a channel portion of the ohmic contact region, being aligned with the end portion of the semiconductor pattern; and   source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes being spaced apart from each other and including first and second thin-film transistor patterns, wherein end portions of the first and second thin film transistor patterns have a stepped portion with respect to each other.   
     
     
         2 . The array substrate of  claim 1 , further comprising:
 a gate line disposed on the base substrate;   a data line disposed on the base substrate on which the gate line is disposed, wherein a first line pattern and a data line pattern form a stepped portion with respect to each other and the first line pattern and the data line pattern cross the gate line; and   a pixel electrode which electrically contacts the drain electrode.   
     
     
         3 . The array substrate of  claim 2 , wherein an end portion of the second thin film transistor pattern is aligned with an end portion of the ohmic contact pattern, and the end portion of the second thin film transistor pattern and an end portion of the first thin film transistor pattern have a stepped portion with respect to each other. 
     
     
         4 . The array substrate of  claim 3 , wherein a first distance between portions of the second thin film transistor pattern corresponding to the source and drain electrodes is greater than a second distance between portions of the first thin film transistor pattern corresponding to the source and drain electrodes.