Method for self aligned metal gate cmos

Abstract

A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.

1 . A method of forming a semiconductor device, the method comprising:
 providing a dual gate semiconductor device structure having FET pair precursors, including an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure;   depositing at least one protective layer across the FET pair precursors, leaving the dummy gate structures exposed;   removing the dummy gate structure from one of the nFET precursor and the pFET precursor to form therein one of an nFET gate hole and a pFET gate hole, respectively;   depositing a first fill into the formed one of the nFET gate hole and the pFET gate hole.   
     
     
         2 . The method of  claim 1 , wherein depositing at least one protective layer includes:
 depositing a first protective layer across the FET pair precursors;   depositing a second protective layer onto the first protective layer; and   removing a portion of the first and second protective layers to expose the dummy gate structures.   
     
     
         3 . The method of  claim 2 , wherein the first protective layer is a SiN liner. 
     
     
         4 . The method of  claim 2 , wherein the second protective layer is a high density plasma oxide. 
     
     
         5 . The method of  claim 1 , wherein the dummy gate structure of the nFET precursor comprises an N-type poly Si, and the dummy gate structure of the pFET precursor comprises a P-type poly Si, and wherein removing the dummy gate structure from one of the nFET precursor and the pFET precursor includes selectively removing the dummy gate structure from one of the nFET precursor and the pFET precursor. 
     
     
         6 . The method of  claim 1 , further comprising, following formation of the pFET gate hole and before depositing the first fill, performing an oxidation treatment. 
     
     
         7 . The method of  claim 1 , wherein depositing the first fill comprises:
 depositing a first conformal film onto the FET pair precursors; and   removing a portion of the first film to expose the first fill and the dummy gate structure from the other of the nFET precursor and the pFET precursor.   
     
     
         8 . The method of  claim 7 , wherein the first conformal film comprises a SiN film. 
     
     
         9 . The method of  claim 7 , further comprising:
 removing the dummy gate structure from the other of the nFET precursor and the pFET precursor to create therein one of the nFET gate hole and the pFET gate hole, respectively; and   depositing a second fill into one of the nFET gate hole and the pFET gate hole.   
     
     
         10 . The method of  claim 9 , further comprising, following formation of the pFET gate hole and before depositing the first fill, performing an oxidation treatment. 
     
     
         11 . The method of  claim 9 , wherein depositing the second fill comprises:
 depositing a second conformal film onto the FET pair precursors; and   removing a portion of the second film to expose the first fill and the second fill.   
     
     
         12 . The method of  claim 11 , wherein the second conformal film comprises a SiN film.