Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making

Abstract

A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

1 - 26 . (canceled) 
     
     
         27 . A method comprising:
 selectively implanting ions into a channel layer of a semiconductor material of a first conductivity type to form implanted gate regions of semiconductor material of a second conductivity type different than the first conductivity type, wherein the channel layer is on an upper surface of a substrate layer and wherein the channel layer comprises a lower surface and one or more raised regions comprising an upper surface and first and second sidewalls, wherein the first and second sidewalls of the raised regions adjacent the lower surface are tapered inward and form an angle of at least 5° from vertical to the upper surface of the substrate, wherein source regions of a semiconductor material of the first conductivity type are on the upper surfaces of the one or more raised regions, the source regions comprising side surfaces adjacent the first and second sidewalls and an upper surface and an implant mask is on the upper surface of the source regions, wherein the implanted gate regions are formed in the sidewalls and in the lower surface of the channel layer and wherein the implanted gate regions are offset from the upper surface of the raised regions; and   removing the implant mask;   wherein the implanted gate regions on the sidewalls are offset from the source layer such that the implanted gate regions on the sidewalls do not contact the source layer.   
     
     
         28 . The method of  claim 27 , wherein an implant blocking layer is on the sidewalls of the raised regions, on side surfaces of the source regions and on side surfaces of the implant mask prior to selectively implanting, the method further comprising removing the implant blocking layer after selectively implanting. 
     
     
         29 . The method of  claim 28 , wherein the implant blocking layer comprises SiO 2 . 
     
     
         30 . The method of  claim 28 , wherein the implant blocking layer is thicker on the side surfaces of the implant mask than on the sidewalls of the raised regions. 
     
     
         31 . The method of  claim 27 , further comprising oxidizing the sidewalls of the raised regions to form oxidized sidewalls prior to selectively implanting, wherein the oxidized sidewalls inhibit implantation in the offset region such that the implanted gate regions are offset from the upper surface of the raised regions by an offset region of semiconductor material of the first conductivity type having a lower doping concentration than the source layer. 
     
     
         32 . The method of  claim 27 , wherein at least a portion of the implant mask is wider than the upper surface of the source regions such that the implant mask overhangs the sidewalls. 
     
     
         33 . The method of  claim 32 , wherein the implant mask comprises a layer of a first material adjacent the source regions and a layer of a second material different than the first material adjacent the layer of the first material, wherein the second material has a higher lateral oxidation rate than the first material, the method further comprising oxidizing the implant mask prior to selectively implanting such that the layer of the second material overhangs the sidewalls. 
     
     
         34 . The method of  claim 33 , wherein the first material is SiO 2  and wherein the second material is Si, GE, or poly-Si or wherein the first material is SiN and the second material is Ge. 
     
     
         35 . The method of  claim 33 , wherein the implant mask is oxidized at temperatures less than 1000° C. 
     
     
         36 . The method of  claim 27 , wherein the side surfaces of the source regions oxidize more rapidly than the gate regions, the method further comprising oxidizing the source and gate regions after selectively implanting, wherein oxidizing recesses the side surfaces of the source layer such that the source layer is separated from the gate regions. 
     
     
         37 . The method of  claim 36 , wherein the semiconductor material of the first conductivity type is an n-type semiconductor material and wherein the semiconductor material of the second conductivity type is a p-type semiconductor material. 
     
     
         38 . The method of  claim 37 , wherein the source regions and/or the gate regions have a doping concentration of at least 1×10 19 . 
     
     
         39 . The method of  claim 27 , wherein the ions are implanted into the channel layer at an angle of +/−2° from vertical to the upper surface of the substrate. 
     
     
         40 . The method of  claim 27 , wherein the first and second sidewalls adjacent the upper surfaces of the one or more raised regions are oriented at an angle of <5° from vertical to the upper surface of the substrate layer. 
     
     
         41 . The method of  claim 27 , wherein the first and second sidewalls adjacent the upper surfaces of the one or more raised regions are oriented at an angle of <2° from vertical to the upper surface of the substrate layer. 
     
     
         42 . The method of  claim 27 , further comprising a drift layer of a semiconductor material of the first conductivity type between the substrate and the channel layer. 
     
     
         43 . The method of  claim 27 , further comprising a buffer layer between the substrate and the channel layer. 
     
     
         44 . The method of  claim 42 , further comprising a buffer layer between the substrate and the drift layer. 
     
     
         45 . The method of  claim 27 , wherein the device comprises a plurality of raised regions, wherein the plurality of raised regions are elongate and are arranged in spaced relationship as fingers. 
     
     
         46 . The method of  claim 27 , wherein the semiconductor material of the first conductivity type is an n-type semiconductor material and wherein the semiconductor material of the second conductivity type is a p-type semiconductor material. 
     
     
         47 . The method of  claim 27 , further comprising:
 forming a gate contact on the lower surface of the channel layer;   forming a source contact on the source layer; and   forming a drain contact on the substrate layer opposite the channel layer.