Implied clock

Abstract

Systems and methods providing clocking between various components or sub-components are shown. Embodiments implement an implied clock technique which reduces the number of signal lines, signaling overhead required for an encoded clock signal, and/or and power consumption for a high speed communication link. In accordance with embodiments efficient communication is provided between a core device and a remote device by the core device providing both clock and data signals to the remote device and the remote device providing a data signal at a predetermined clock rate without communicating its clock signal. The core device of this embodiment determines an “implied clock” suitable for accurately receiving data from the remote device.

1 . A method of serial communication between a core device and a remote device comprising the steps of:
 transmitting a predetermined bit pattern within a data stream from the remote device to the core device, said data stream being at a known clock rate;   determining a range of clock signal phases for sampling the data stream to yield the predetermined bit pattern;   selecting a phase from within the range of clock signal phases; and   sampling the data stream utilizing the known clock rate and the selected phase to communicate data between the remote device and the core device.   
     
     
         2 . The method of  claim 1 , wherein the step of determining includes the steps of selecting a clock phase, sampling the data stream from the remote device utilizing the selected clock phase, and comparing a sampled value to the predetermined bit pattern. 
     
     
         3 . The method of  claim 2 , wherein the step of determining includes repeated steps of selecting different phases and sampling the data stream utilizing the different phases. 
     
     
         4 . The method of  claim 1 , wherein the step of selecting a phase includes selecting an optimum value of the range of phases. 
     
     
         5 . The method of  claim 1 , wherein the data stream includes repeated predetermined bit patterns during the step of determining a range of clock signal phases. 
     
     
         6 . The method of  claim 5 , wherein the predetermined bit patterns separate messages within the data stream having a defined or predictable message size. 
     
     
         7 . The method of  claim 1 , further comprising the step of: transmitting a data signal and a clock signal from the core device to the remote device. 
     
     
         8 . The method of  claim 7 , wherein the known clock rate is a multiple or division of a clock signal transmitted from the core device to the remote device. 
     
     
         9 . The method of  claim 7 , wherein the data signal and the clock signal are transmitted to the remote device on separate data lines. 
     
     
         10 . The method of  claim 1 , wherein the remote device includes a plurality of separate remote devices and the steps of transmitting, determining, selecting and sampling are performed in association with each of the plurality of separate remote devices. 
     
     
         11 . The method of  claim 1 , wherein the core device includes a controller and the remote device includes a transducer unit of an ultrasound device. 
     
     
         12 . The method of  claim 11 , wherein the ultrasound device is a hand-held, battery powered device. 
     
     
         13 . A serial communications system comprising:
 a clock signal circuit for transmitting a clock signal from a core device;   a remote device receiving the clock signal and transmitting a predetermined data signal within a data stream to the core device at a known clock rate;   a link initializer circuit which determines a range of clock signal phases for sampling the data stream to yield the predetermined data signal;   a phase selection circuit which determines a preferred clock signal phase within the range of clock signal phases; and   a data sampler using clock signal and designated phase information to sample the data stream.   
     
     
         14 . The system of  claim 13 , wherein the link initializer circuit selects a clock phase, samples the data stream from the remote device utilizing the selected clock phase, and compares a sampled value to the predetermined data signal. 
     
     
         15 . The system of  claim 14 , wherein the link initializer circuit repeatedly selects different phases and samples the data stream utilizing the different phases. 
     
     
         16 . The system of  claim 13 , wherein the phase selection circuit selects an optimum value of the range of clock signal phases. 
     
     
         17 . The system of  claim 13 , wherein the known clock rate is a multiple or division of the clock signal transmitted from the clock signal circuit. 
     
     
         18 . The system of  claim 13 , wherein the predetermined data signal separates messages within the data stream having a defined or predictable message size. 
     
     
         19 . A serial communication system comprising:
 means for transmitting a clock signal from a core device;   means for receiving the clock signal at a remote device;   means for transmitting a predetermined data signal from the remote device to the core device at a known clock rate;   means for determining a range of clock signal phases for sampling the data stream to yield the predetermined data signal;   means for selecting a phase from within the range of clock signal phases; and   means for sampling the data stream using the known clock rate and the selected phase.   
     
     
         20 . The system of  claim 19 , wherein the means for determining a range of clock signal phases includes means for selecting a clock phase, means for sampling the data stream from the remote device utilizing a selected clock phase, and means for comparing a sampled value to the predetermined bit pattern. 
     
     
         21 . The system of  claim 20 , wherein the means for determining the range includes means for repeatedly selecting different phases and means for repeatedly sampling the data stream utilizing the different phases. 
     
     
         22 . The system of  claim 19 , wherein the means for selecting a phase selects an optimum value of the range of phases. 
     
     
         23 . A signal processor for an ultrasonic device comprising:
 an ultrasonic transducer having a clock signal receiving circuit and a transmitter for sending a predetermined data signal at a known clock rate to a controller;   a link initializer circuit which determines a range of clock phases for sampling the data stream to yield the predetermined data signal;   a phase selection circuit which selects a preferred clock phase from within the range of clock phases; and   a data sampler using the known clock rate and the preferred clock phase to sample the data stream to communicate data from the ultrasonic transducer to the controller.   
     
     
         24 . The signal processor of  claim 23 , wherein the ultrasonic transducer and controller are associated with a hand-held, battery powered device. 
     
     
         25 . The signal processor of  claim 23 , wherein the link initializer circuit selects a clock phase, samples the data stream from the transducer utilizing the selected clock phase, and compares a sampled value to the predetermined bit pattern. 
     
     
         26 . The signal processor of  claim 23 , wherein the link initializer circuit repeatedly selects different phases and samples the data stream utilizing the different phases. 
     
     
         27 . The signal processor of  claim 23 , wherein the phase selection circuit selects a optimum value of the range of clock signal phases. 
     
     
         28 . A serial communication system for an ultrasonic diagnostic device comprising:
 means for transmitting a clock signal to an ultrasonic transducer;   means for receiving the clock signal at the ultrasonic transducer;   means for transmitting a predetermined data signal from the ultrasonic transducer to a controller at a known clock rate;   means for determining a range of clock signal phases for sampling the data stream from the ultrasonic device to yield the predetermined data signal;   means for selecting a phase from within the range of clock signal phases; and   means for sampling the data stream from the ultrasonic transducer using the known clock rate and the selected phase.   
     
     
         29 . The serial communication system of  claim 28 , wherein the means for determining a range of clock signal phases selects a clock phase, samples the data stream from the ultrasonic transducer utilizing a selected clock phase, and compares a sampled value to the predetermined bit pattern. 
     
     
         30 . The serial communication system of  claim 29 , wherein the means for determining the range repeatedly selects different phases and repeatedly samples the data stream utilizing the different phases.