Semiconductor device

Abstract

The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type, body regions of a second conductivity type plurally formed on a surface layer portion of the semiconductor layer at an interval, a source region of the first conductivity type formed on a surface layer portion of each body region, a gate insulating film provided on the semiconductor layer to extend between the body regions adjacent to each other, a gate electrode provided on the gate insulating film and opposed to the body regions, and a field relaxation portion provided between the body regions adjacent to each other for relaxing an electric field generated in the gate insulating film.

1 . A semiconductor device comprising:
 a semiconductor layer of a first conductivity type;   body regions of a second conductivity type plurally formed on a surface layer portion of the semiconductor layer at an interval;   a source region of the first conductivity type formed on a surface layer portion of each body region;   a gate insulating film provided on the semiconductor layer to extend between the body regions adjacent to each other;   a gate electrode provided on the gate insulating film and opposed to the body regions; and   a field relaxation portion provided between the body regions adjacent to each other for relaxing an electric field generated in the gate insulating film.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein
 when noting three body regions and assuming a plurality of straight lines extending between the adjacent body regions, the field relaxation portion includes a dotlike field relaxation portion provided on the intersection point between two straight lines included in the straight lines.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein
 the field relaxation portion includes a linear field relaxation portion provided on a portion along the straight lines.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein
 the dotlike field relaxation portion has a sectional area greater than the sectional area of the linear field relaxation portion in an orthogonal direction orthogonal to the straight lines.   
     
     
         5 . The semiconductor device according to  claim 2 , wherein
 the dotlike field relaxation portion overlaps with the body regions in plan view.   
     
     
         6 . The semiconductor device according to  claim 2 , wherein
 the dotlike field relaxation portion is in the form of a square in plan view.   
     
     
         7 . The semiconductor device according to  claim 3 , wherein
 the linear field relaxation portion is formed to separate from the dotlike field relaxation portion.   
     
     
         8 . The semiconductor device according to  claim 2 , wherein
 when four body regions are arrayed in the form of a matrix of two rows and two columns in plan view,   the dotlike field relaxation portion is provided on a position overlapping with a region where a line region extending between the respective ones of the body regions in the form of the matrix in a row direction and a line region extending between the body regions in a column direction intersect with each other in plan view.   
     
     
         9 . The semiconductor device according to  claim 1 , wherein
 when the body regions are elongationally formed and arrayed along the width direction orthogonal to the longitudinal direction thereof,   the field relaxation portion is provided on a position overlapping with a longitudinal end portion of a line region extending between the body regions adjacent to each other along the longitudinal direction in plan view.   
     
     
         10 . The semiconductor device according to  claim 9 , wherein
 the field relaxation portion is further provided on a portion along the line region.   
     
     
         11 . The semiconductor device according to  claim 1 , wherein
 the plane area of the field relaxation portion is smaller than the plane area of the body regions.   
     
     
         12 . The semiconductor device according to  claim 1 , wherein
 the field relaxation portion includes an implantation region formed by implanting a second conductivity type impurity between the body regions adjacent to each other on the semiconductor layer.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein
 the implantation region is formed by implanting Al or B as the second conductivity type impurity.   
     
     
         14 . The semiconductor device according to  claim 12 , wherein
 the implantation region is increased in resistance due to the implantation of the second conductivity type impurity into the semiconductor layer.   
     
     
         15 . The semiconductor device according to  claim 14 , wherein
 the implantation region is increased in resistance due to implantation of Al, B, Ar or V.   
     
     
         16 . The semiconductor device according to  claim 1 , wherein
 the gate insulating film has a relatively thin thin-film portion opposed to the body regions, and a relatively thick thick-film portion as the field relaxation portion opposed to a portion of the semiconductor layer located between the body regions.   
     
     
         17 . The semiconductor device according to  claim 1 , wherein
 the gate electrode has a through-hole in a portion opposed to a portion of the semiconductor layer located between the body regions, and   the semiconductor device includes an interlayer dielectric film formed on the semiconductor layer to cover the gate electrode and having an embedded portion as the field relaxation portion embedded in the through-hole.   
     
     
         18 . The semiconductor device according to  claim 1 , wherein
 the gate insulating film has a low dielectric constant portion opposed to the body regions and a high dielectric constant portion as the field relaxation portion opposed to a portion of the semiconductor layer located between the body regions.   
     
     
         19 . The semiconductor device according to  claim 1 , wherein
 the semiconductor layer has a protrusion as the field relaxation portion formed by raising the surface thereof between the body regions.   
     
     
         20 . The semiconductor device according to  claim 19 , wherein
 the second conductivity type impurity is implanted into the protrusion.   
     
     
         21 . The semiconductor device according to  claim 19 , wherein
 the gate insulating film has a low dielectric constant portion opposed to the body regions and a high dielectric constant portion as the field relaxation portion covering the protrusion.   
     
     
         22 . The semiconductor device according to  claim 21 , wherein
 the high dielectric constant portion is formed to cover the protrusion and to be opposed to the body regions, and   the low dielectric constant portion is interposed between the body regions and a portion of the high dielectric constant portion opposed to the body regions.   
     
     
         23 . The semiconductor device according to  claim 21 , wherein
 the low dielectric constant portion is formed to be opposed to the body regions and to cover the protrusion, and   the high dielectric constant portion is interposed between the protrusion and a portion of the low dielectric constant portion covering the protrusion.   
     
     
         24 . The semiconductor device according to  claim 12 , wherein
 the gate insulating film has a relatively thin thin-film portion opposed to the body regions and a relatively thick thick-film portion opposed to the implantation region on the semiconductor layer, and   the implantation region and the thick-film portion are constituted as the field relaxation portion.   
     
     
         25 . The semiconductor device according to  claim 12 , wherein
 the gate electrode has a through-hole in a portion opposed to the implantation region on the semiconductor layer,   an interlayer dielectric film having an embedded portion embedded in the through hole is formed on the semiconductor layer to cover the gate electrode, and   the implantation region and the embedded portion are constituted as the field relaxation portion.   
     
     
         26 . The semiconductor device according to  claim 12 , wherein
 the gate insulating film has a low dielectric constant portion opposed to the body regions and a high dielectric constant portion opposed to the implantation region on the semiconductor layer, and   the implantation region and the high dielectric constant portion are constituted as the field relaxation portion.   
     
     
         27 . The semiconductor device according to  claim 1 , wherein
 the semiconductor layer has a dielectric breakdown field of not less than 1 MV/cm.   
     
     
         28 . The semiconductor device according to  claim 27 , wherein
 the semiconductor layer is made of SiC.   
     
     
         29 . The semiconductor device according to  claim 1 , wherein
 the body regions are in the form of regular polygons in plan view.   
     
     
         30 . The semiconductor device according to  claim 29 , wherein
 the body regions are in the form of squares in plan view.   
     
     
         31 . The semiconductor device according to  claim 29 , wherein
 the body regions are in the form of regular hexagons in plan view, and the regular-hexagonal body regions are arrayed in the form of a honeycomb.   
     
     
         32 . The semiconductor device according to  claim 1 , wherein
 the body regions are in the form of circles in plan view.