Method of processing faults in a microcontroller

Abstract

Embodiments described in the present disclosure relate to a method of processing faults in a control unit, the method including: upon each request for reading a datum in a first memory, received by a first interface circuit for accessing the first memory, calculating by means of the first interface circuit, a check word based on the datum read, if the check word calculated is different from a check word read in the memory in association with the datum read, activating an error signal by means of the first interface circuit, and sending the error signal to an output circuit of the control unit, without using any circuits of the control unit, likely to send a request to access the first memory.

1 . A method to process faults in a control unit, the method comprising:
 upon each request to read a datum in a first memory, received by a first interface circuit configured to access the first memory, calculating by the first interface circuit a check word based on the datum read;   if the calculated check word is different from a check word read in the first memory in association with the datum read, activating by the first interface circuit an error signal; and   sending the error signal to an output circuit of the control unit without using other circuits of the control unit configured to send a request to access the first memory.   
     
     
         2 . A method according to  claim 1 , comprising applying a parity calculation by the first interface circuit to the datum read to calculate the check word. 
     
     
         3 . A method according to  claim 1 , comprising:
 upon each request for reading a second datum in a second memory, received by a second interface circuit configured to access the second memory, detecting errors in the second datum read by the second interface circuit using error-correction bits read in the second memory in association with the second datum read;   if non-correctable errors are detected by the second interface circuit in the second datum read, activating a second error signal by the second interface circuit; and   sending the second error signal from the second interface circuit to the output circuit without using other circuits of the control unit configured to send a request to access the second memory.   
     
     
         4 . A method according to  claim 1  wherein the output circuit is configured to receive at least one other error signal of a plurality of error signals, the at least one other error signal drawn from the group of a control unit power supply error signal, a comparison signal for comparing an input signal of the control unit with a threshold, a hardware error signal, an emergency stop manual trigger signal, and a system clock error signal of the control unit. 
     
     
         5 . A method according to  claim 4  wherein each error signal is sent to the output circuit if each respective error signal is not masked by a masking circuit. 
     
     
         6 . A method according to  claim 5 , comprising:
 initializing the masking circuit to an unmasked state wherein each respective error signal of the plurality of error signals is passable to the output circuit;   masking at least one of the plurality of error signals; and   prohibiting the unmasking of the at least one of the plurality of error signals to prevent being passable again to the output circuit the at least one of the plurality of error signals that was masked.   
     
     
         7 . A method according to  claim 1 , comprising:
 executing by the output circuit a procedure to stop power circuits linked to the output circuit, the procedure triggered by the output circuit receiving the error signal.   
     
     
         8 . A control unit, comprising:
 at least one circuit configured to send a request to read a datum in a first memory;   a first interface circuit configured to access the first memory, configured to calculate a check word based on the datum read, and configured, if the calculated check word is different from a check word read in the first memory in association with the datum read, to activate an error signal;   an output circuit; and   an error management circuit configured to send the error signal to the output circuit without using other circuits of the control unit that are configured to send the request to access the first memory.   
     
     
         9 . A control unit according to  claim 8  wherein the first memory is a volatile memory. 
     
     
         10 . A control unit according to  claim 8  comprising:
 a second interface circuit configured to access a second memory. 
 
     
     
         11 . A control unit according to  claim 10  wherein the second memory is a non-volatile memory. 
     
     
         12 . A control unit according to  claim 10 , comprising:
 a plurality of circuits, each circuit of the plurality of circuits configured to send a request to access the first or the second memory, the plurality of circuits including a processing unit and at least one transfer circuit configured to transfer data blocks to or from the first memory or the second memory.   
     
     
         13 . A control unit according to  claim 8 , comprising:
 an error signal masking circuit configured to send only unmasked error signals to the output circuit.   
     
     
         14 . A control unit according to  claim 13  wherein the error signal masking circuit is configured to receive at least one other error signal of a plurality of error signals, the at least one other error signal drawn from the group of a control unit power supply error signal, a comparison signal for comparing an input signal of the control unit with a threshold, a hardware error signal, an emergency stop manual trigger signal, and a system clock error signal of the control unit. 
     
     
         15 . An apparatus comprising:
 power circuits;   power switches; and   a control unit, the control unit including:
 an output circuit linked to the power circuits via the power switches; and 
 an interface circuit coupled to a memory, the interface circuit configured to read a datum in the memory and configured to read a check word in memory associated with the datum, the interface circuit configured to calculate a check word based on the datum, and the interface circuit configured, if the calculated check word is different from the read check word, to activate an error signal, the error signal configured for passage to at least one power switch. 
   
     
     
         16 . An apparatus according to  claim 15  wherein the output circuit is configured to execute a procedure to stop at least one power circuit upon receiving the error signal. 
     
     
         17 . An apparatus according to  claim 15 , the control unit including:
 a second interface circuit coupled to a second memory.   
     
     
         18 . An apparatus according to  claim 17  wherein at least one of the first memory and second memory is an external memory coupled to the apparatus. 
     
     
         19 . An apparatus according to  claim 17 , the control unit including:
 a plurality of circuits, each circuit of the plurality of circuits configured to send a request to access the first memory or the second memory, the plurality of circuits including a processing unit and at least one transfer circuit configured to transfer data blocks to or from the first memory or the second memory.   
     
     
         20 . An apparatus according to  claim 16 , the control unit including:
 an error signal masking circuit configured to send only unmasked error signals to the output circuit.   
     
     
         21 . An apparatus according to  claim 16  wherein the error signal masking circuit is configured to receive at least one other error signal of a plurality of error signals, the at least one other error signal drawn from the group of a control unit power supply error signal, a comparison signal for comparing an input signal of the control unit with a threshold, a hardware error signal, an emergency stop manual trigger signal, and a system clock error signal of the control unit.