Memory device including a memory block having a fixed latency data output

Abstract

A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to receiving a read command and being clocked by a first clock signal having a selectable delay dependent upon a propagation delay for the read data to be output by a memory core. The clock generation unit is configured to generate a second clock signal having a selectable delay based on a system clock signal. The read data provided by the memory block in response to the second clock signal such that the read data has a latency that approximately the same, or is relatively fixed, for different frequencies of the system clock signal.

1 . A memory block comprising:
 a memory circuit including a memory core configured to output read data in response to receiving a read command, the memory circuit further configured to output the read data in response to a first clock signal having a selectable delay based on a propagation delay of the read data in the memory core;   a clock generation unit configured to generate a second clock signal having a selectable delay based on a system clock signal; and   a data output unit coupled to the memory core and configured to output the read data from the memory block in response to the second clock signal such that the read data output from the memory block has a latency from when the read command is received at the memory block, wherein the latency is relatively fixed for different frequencies of the system clock signal.   
     
     
         2 . The memory block of  claim 1  wherein the latency is approximately the same for different frequencies of the system clock signal. 
     
     
         3 . The memory block of  claim 1 , wherein the first clock signal operates at a frequency multiple of the system clock signal that is less than one. 
     
     
         4 . The memory block of  claim 1 , wherein the memory circuit is configured to select a delay of the first clock signal in response to receiving a delay select signal. 
     
     
         5 . The memory block of  claim 4 , wherein the delay select signal corresponds to a delay value which compensates for variations in time for the read data to be output by the memory core after the read command is received at the memory block when the memory block is operated across process, voltage, or temperature variations. 
     
     
         6 . The memory block of  claim 1 , wherein the memory circuit is configured to adjust a delay of the first clock signal dynamically during operation of the memory block to compensate for variations in time for the read data to be output by the memory core after the read command is received at the memory block when the memory block is operated across process, voltage, or temperature variations. 
     
     
         7 . The memory block of  claim 1 , wherein the system clock signal includes a plurality of clock edges, and wherein the clock generation unit is further configured to select a delay of the second clock signal by selecting a clock edge from the plurality of clock edges of the system clock signal. 
     
     
         8 . The memory block as recited in  claim 7 , wherein the clock generation unit is further configured to select the clock edge from the plurality of clock edges in response to receiving a data clock select signal. 
     
     
         9 . The memory block as recited in  claim 1 , wherein the memory circuit is configured to select a delay of the second clock signal dynamically during operation of the memory block to compensate for variations in time for the read data to be output by the memory core after the read command is received at the memory block when the memory block is operated across process, voltage, or temperature variations. 
     
     
         10 . A method comprising:
 outputting read data from a memory core of a memory circuit in response to receiving a read command at a memory block including the memory circuit;   outputting the read data from the memory circuit in response to a first clock signal having a selectable delay based on a propagation delay of the read data in the memory core;   generating a second clock signal having a selectable delay based on a system clock signal; and   outputting the read data from the memory block including the memory circuit in response to the second clock signal such that the read data output from the memory block has a latency from when the read command is received at the memory block, wherein the latency is relatively fixed for different frequencies of the system clock signal.   
     
     
         11 . The method  claim 10 , wherein the first clock signal operates at a frequency multiple of the system clock signal that is less than one. 
     
     
         12 . The method  claim 10 , further comprising:
 selecting a delay of the first clock signal in response to receiving a delay select signal at the memory circuit.   
     
     
         13 . The method  claim 12 , wherein the delay select signal corresponds to a delay value which compensates for variations in time for the read data to be output by the memory core after the read command is received at the memory circuit when the memory block is operated across process, voltage, or temperature variations. 
     
     
         14 . The method of  claim 10 , further comprising:
 adjusting a delay of the first clock signal dynamically during operation of the memory block to compensate for variations in time for the read data to be output by the memory core after the read command is received at the memory block when the memory block is operated across process, voltage, or temperature variations.   
     
     
         15 . The method of  claim 10 , wherein the system clock signal includes a plurality of clock edges, the method further comprising:
 selecting a delay of the second clock signal by selecting a clock edge from the plurality of clock edges of the system clock signal.   
     
     
         16 . The method of  claim 15 , wherein selecting the delay of the second clock signal is performed in response to receiving a data clock select signal. 
     
     
         17 . The method of  claim 10 , further comprising:
 selecting a delay of the second clock signal dynamically during operation of the memory block to compensate for variations in time for the read data to be output by the memory core after the read command is received at the memory block when the memory block is operated across process, voltage, or temperature variations.   
     
     
         18 . A system comprising:
 a memory block comprising:
 a memory circuit including a memory core configured to output read data in response to receiving a read command, the memory circuit further configured to output the read data in response to a first clock signal having a selectable delay based on a propagation delay of the read data in the memory core; 
 a clock generation unit configured to generate a second clock signal having a selectable delay based on a system clock signal; and 
 a data output unit coupled to the memory core and configured to output the read data from the memory block in response to the second clock signal such that the read data output from the memory block has a latency from when the read command is received at the memory block, wherein the latency is relatively fixed for different frequencies of the system clock signal; and 
   a memory controller coupled to the memory block, the memory controller including a storage configured to store clock configuration information, wherein the memory controller is configured to use the clock configuration information to generate clock select signals for selecting a delay of the second clock signal.   
     
     
         19 . The system as recited in  claim 18 , wherein the clock configuration information includes a lookup table having respective entries corresponding to different operating frequencies of the system clock signal, wherein each entry includes an encoding that corresponds to the clock select signals. 
     
     
         20 . The system as recited in  claim 19 , wherein the memory controller is further configured to provide additional delay select signals to delay the first clock signal dynamically during operation of the memory block. 
     
     
         21 . The system as recited in  claim 18 , wherein the first clock signal is derived from, and operates at, a frequency multiple of the system clock signal that is less than one.