8t sram cell with higher voltage on the read wl

Abstract

The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.

1 - 14 . (canceled) 
     
     
         15 . An integrated circuit including:
 an SRAM cell comprising:
 a first inverter comprising a first load transistor and a first driver transistor, the first inverter having a first input formed by a connection between a gate of the first load transistor and a gate of the first driver transistor, and having a first output formed by a connection between a first source or drain of the first load transistor and a first source or drain of the first driver transistor; 
 a second inverter comprising a second load transistor and a second driver transistor, the second inverter having a second input formed by a connection between a gate of the second load transistor and a gate of the second driver transistor, and having a second output formed by a connection between a first source or drain of the second load transistor and a first source or drain of the second driver transistor; the second input being connected to the first output, and the second output being connected to the first input; 
 a first write transistor connected between the first output and a write bit-line, and having a gate connected to a write wordline; and 
 a second write transistor connected between the second output and a complementary write bit-line, and having a gate connected to the write wordline; and 
   an assist circuit comprising:
 a first assist circuit transistor having a first source or drain connected to a read bit-line, and a gate connected to a read wordline or the write wordline; and 
 a second assist circuit transistor having a gate connected to one of the first and second outputs, a first source or drain connected to a second source or drain of the first assist circuit transistor, and a second source or drain connected to a second source or drain of each of the first and second driver transistors. 
   
     
     
         16 . The circuit of  claim 15 , wherein the first and second load transistors are pMOS transistors and the first and second driver transistors are nMOS transistors. 
     
     
         17 . The circuit of  claim 16 , wherein the first and second write transistors are nMOS transistors. 
     
     
         18 . The circuit of  claim 17 , wherein the first assist circuit transistor and the second assist circuit transistor are nMOS transistors. 
     
     
         19 . The circuit of  claim 18 , wherein the first assist circuit transistor gate is attached to the read wordline. 
     
     
         20 . The circuit of  claim 18 , wherein the first assist circuit transistor gate is attached to the write wordline. 
     
     
         21 . The circuit of  claim 18 , wherein the second assist circuit transistor gate is connected to the first output. 
     
     
         22 . The circuit of  claim 21 , further including a voltage supply circuit comprising a diode-configured transistor connected between a supply voltage node and the second source or drain of each of the first and second driver transistors. 
     
     
         23 . The circuit of  claim 15 , wherein the first assist circuit transistor and the second assist circuit transistor are nMOS transistors. 
     
     
         24 . The circuit of  claim 23 , wherein the second assist circuit transistor gate is connected to the first output. 
     
     
         25 . The circuit of  claim 23 , further including a voltage supply circuit comprising a diode-configured transistor connected between a supply voltage node and the second source or drain of each of the first and second driver transistors. 
     
     
         26 . The circuit of  claim 15 , further including a voltage supply circuit comprising a diode-configured transistor connected between a supply voltage node and the second source or drain of each of the first and second driver transistors. 
     
     
         27 . The circuit of  claim 15 , wherein the first assist circuit transistor gate is attached to the read wordline. 
     
     
         28 . The circuit of  claim 15 , wherein the first assist circuit transistor gate is attached to the write wordline. 
     
     
         29 . An integrated circuit including:
 an SRAM cell comprising:
 a first inverter comprising a first load transistor and a first driver transistor, the first inverter having a first input formed by a connection between a gate of the first load transistor and a gate of the first driver transistor, and having a first output formed by a connection between a first source or drain of the first load transistor and a first source or drain of the first driver transistor; 
 a second inverter comprising a second load transistor and a second driver transistor, the second inverter having a second input formed by a connection between a gate of the second load transistor and a gate of the second driver transistor, and having a second output formed by a connection between a first source or drain of the second load transistor and a first source or drain of the second driver transistor; the second input being connected to the first output, and the second output being connected to the first input; 
 a first write transistor connected between the first output and a write bit-line, and having a gate connected to a write wordline; and 
 a second write transistor connected between the second output and a complementary write bit-line, and having a gate connected to the write wordline; 
   a first read circuit comprising:
 a first read transistor having a first source or drain connected to a read bit-line, and a gate connected to a read wordline; and 
 a first read driver transistor having a gate connected to one of the first and second outputs, a first source or drain connected to a second source or drain of the first read transistor, and a second source or drain connected to a second source or drain of each of the first and second driver transistors; and 
   a second read circuit comprising:
 a second read transistor having a first source or drain connected to a complementary read bit-line, and a gate connected to the read wordline; and 
 a second read driver transistor having a gate connected to the other one of the first and second outputs, a first source or drain connected to a second source or drain of the second read transistor, and a second source or drain connected to the second source or drain of each of the first and second driver transistors. 
   
     
     
         30 . The circuit of  claim 29 , wherein the first and second load transistors are pMOS transistors and the first and second driver transistors are nMOS transistors. 
     
     
         31 . The circuit of  claim 30 , wherein the first and second write transistors are nMOS transistors. 
     
     
         32 . The circuit of  claim 31 , wherein the first and second read transistors and the first and second read driver transistors are nMOS transistors. 
     
     
         33 . The circuit of claim  320 , wherein the first read driver transistor gate is connected to the first output and the second read driver transistor gate is connected to the second output. 
     
     
         34 . The circuit of  claim 29 , wherein the first and second read transistors and the first and second read driver transistors are nMOS transistors.