Method and structure of forming silicide and diffusion barrier layer with direct deposited film on si

Abstract

A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

1 . A semiconductor device having a contact structure, which comprises:
 a silicon (Si) substrate;   a metal alloy layer directly deposited on the silicon substrate;   a metal silicide layer and a diffusion barrier layer formed simultaneously from thermal annealing the metal alloy layer; and   a metal layer deposited on the silicide and barrier layers.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the Si substrate is made of one selected from the group consisting of monocrystalline Si, polycrystalline Si, doped Si, amorphous Si, Si x Ge 1-x  where x is any number satisfying 0<x<1, Si x N 1-x  where x is any number satisfying 0<x<1, and SiC. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the metal alloy layer(s) is made of at least one metal selected from the group consisting of Ni, Co, Pt, Pd, Ta, Ti, Nb, V, Hf, Zr, Mo, W and alloys thereof. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the metal layer comprises Ni and W, or is a composition gradient of Ni and W. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the metal layer deposited on of the silicide and barrier layers is Cu, Ni, Co, Ag, or Au. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the metal silicide layer is a nickel silicide layer. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the diffusion barrier layer has a thickness of about 0.1 to 10 nm. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein the metal alloy layer has a thickness of about 1 to 1,000 nm, with 10 to 200 nm being more typical. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein the metal layer is annealed at a temperature of about 100° C. to 1,000° C., with 200° C. to 600° C. being more typical. 
     
     
         10 . The semiconductor device according to  claim 1 , wherein the metal alloy layer is deposited by electrodeposition, e-beam evaporation, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), or sputtering. 
     
     
         11 . The semiconductor device according to  claim 1 , wherein the semiconductor device is a complementary metal oxide silicon (CMOS) logic device, a memory device, an embedded memory device, or a photovoltaic cell.