Wafer level embedded and stacked die power system-in-package packages

Abstract

Wafer level embedded and stacked die power system-in-package semiconductor devices, and methods for making and using the same, are described. The methods include placing a first side of a substrate frame, which includes through cavity and an adjacent via, on a carrier. A first side of a component selected from an active device and a passive device can be placed on the carrier, within the cavity. A perimeter of the cavity can be attached to a perimeter of the component. Material at a second side of the substrate frame can be removed so the via extends from the frame's first side to the frame's second side. The substrate frame and component can then be removed from the carrier so that routing can be distributed between the first side of the frame and the first side of the component to electrically connect the component with the via. Other embodiments are described.

1 .- 22 . (canceled) 
     
     
         23 . A semiconductor package, comprising:
 a substrate frame having a cavity and a through-via between a first side of the substrate frame and a second side opposite the first side;   an active device having a first side and a second side, wherein the active device is located within the cavity of the substrate frame so that a perimeter of the active device is adjacent a perimeter of the substrate frame cavity; and   routing disposed across a portion of the first side of the active device and the first side of the substrate frame to electrically connect the active device to the through-via.   
     
     
         24 . The package of  claim 23 , wherein the substrate frame comprises glass, silicon, a pre-molded epoxy molding compound, or combinations thereof. 
     
     
         25 . The package of  claim 23 , wherein the substrate frame comprises glass. 
     
     
         26 . The package of  claim 23 , wherein a passive device is stacked on and electrically connected to a portion of the first side of the active device. 
     
     
         27 . The package of  claim 23 , wherein multiple passive devices are stacked on and electrically connected to the first side of the active device. 
     
     
         28 . The package of  claim 23 , wherein a bump is connected to the through-via at the second side of the substrate frame. 
     
     
         29 . The package of  claim 23 , wherein the perimeter of the active device and the perimeter of the cavity are separated by an epoxy. 
     
     
         30 . A semiconductor package, comprising:
 a substrate frame having a cavity and a through-via between a first side of the substrate frame and a second side opposite the first side;   a passive device having a first side and a second side, wherein the passive device is located within the cavity of the substrate frame so that a perimeter of the passive device is adjacent a perimeter of the substrate frame cavity; and   routing disposed across a portion of the first side of the passive device and the first side of the substrate frame to electrically connect the passive device to the through-via.   
     
     
         31 . The package of  claim 30 , wherein the substrate frame comprises glass, silicon, a pre-molded epoxy molding compound, or combinations thereof. 
     
     
         32 . The package of  claim 30 , wherein the substrate frame comprises glass. 
     
     
         33 . The package of  claim 30 , wherein an active device is stacked on and electrically connected to a portion of the first side of the passive device. 
     
     
         34 . The package of  claim 30 , wherein multiple active devices are stacked on and electrically connected to the first side of the passive device. 
     
     
         35 . The package of  claim 30 , wherein a bump is connected to the through-via at the second side of the substrate frame. 
     
     
         36 . The package of  claim 30 , wherein the perimeter of the passive device and the perimeter of the cavity are separated by an epoxy. 
     
     
         37 . A semiconductor package, comprising:
 a substrate frame having a cavity and a through-via between a first side of the substrate frame and a second side opposite the first side;   a die containing an integrated circuit having a first side and a second side, wherein the die is located within the cavity of the substrate frame so that a perimeter of the die is adjacent a perimeter of the substrate frame cavity; and   routing disposed across a portion of the first side of the die and the first side of the substrate frame to electrically connect the integrated circuit to the through-via.   
     
     
         38 . The package of  claim 37 , wherein the substrate frame comprises glass. 
     
     
         39 . The package of  claim 37 , wherein the integrated circuit in the die comprises a passive device and an active device is stacked on and electrically connected to a portion of the first side of the passive device. 
     
     
         40 . The package of  claim 37 , wherein the integrated circuit in the die comprises an active device and a passive device is stacked on and electrically connected to a portion of the first side of the active device. 
     
     
         41 . The package of  claim 37 , wherein a bump is connected to the through-via at the second side of the substrate frame. 
     
     
         42 . The package of  claim 37 , wherein the perimeter of the die and the perimeter of the cavity are separated by an epoxy.