Semiconductor device, lower layer wiring designing device, method of designing lower layer wiring and computer program

Abstract

A semiconductor device includes a lower wiring layer including a plurality of lower wirings, each of the lower wirings being elongated to run substantially parallel to a first direction, a metal-insulator-metal (MIM) capacitor formed above the plurality of lower wirings, the MIM capacitor comprising lower and upper electrodes and a capacity dielectric film interposed between the lower and upper electrodes, and an upper wiring layer formed above the MIM capacitor, the upper wiring layer including a plurality of upper wirings which are connected to the lower and upper electrodes through a plurality of first via plus and a plurality of second via plugs, respectively. Each of the plurality of first via plugs and the plurality of second via plugs are arranged parallel to the first direction, and the plurality of second via plus is arranged above portions between the lower wirings.

1 . A semiconductor device comprising:
 a lower wiring layer including a plurality of lower wirings, each of the lower wirings being elongated to run substantially parallel to a first direction;   a metal-insulator-metal (MIM) capacitor formed above the plurality of lower wirings, the MIM capacitor comprising:
 lower and upper electrodes; and 
 a capacity dielectric film interposed between the lower and upper electrodes; and 
   an upper wiring layer formed above the MIM capacitor, the upper wiring layer including a plurality of upper wirings which are connected to the lower and upper electrodes through a plurality of first via plug and a plurality of second via plugs, respectively,   wherein each of the plurality of first via plugs and the plurality of second via plugs is arranged parallel to the first direction, and the plurality of second via plug is arranged above portions between the lower wirings.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the plurality of first via plugs are arranged without overlapping with the plurality of lower wirings in a planar view. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein a plane of the upper electrode has a rectangular shape, and the plurality of lower wirings are not arranged right below one or more than one edge of the plane of the upper electrode. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the upper electrode comprises a planar form which is smaller than a planar form of the lower electrode. 
     
     
         5 . The semiconductor device according to  claim 1 , further comprising a wiring cap film formed between the lower wiring layer and the lower electrode.