Enhancing mosfet performance by optimizing stress properties

Abstract

A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas formed in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.

1 . A semiconductor device having improved performance, comprising:
 a gate structure formed on a substrate, the gate structures being formed in an operative relationship with active areas formed in the substrate;   a stress liner formed on the gate structure, the stress liner including stress relieved vertical surfaces wherein portions of the stress liner in contact with the active areas which are shielded from the ions due to a shadowing effect during ion implantation maintain as-deposited stresses.   
     
     
         2 . The device as recited in  claim 1 , further comprising dummy structures formed at a periphery of an array of gate structures to provide the shadowing effect for gate structures adjacent to the periphery of the array of gate structures. 
     
     
         3 . The device as recited in  claim 1 , wherein the gate structures include gate structures for N-type field effect transistors. 
     
     
         4 . The device as recited in  claim 1 , further comprising a P-type field effect transistor having a transverse compressive stress relieved stress liner on associated gate structures. 
     
     
         5 . The device as recited in  claim 1 , wherein the gate structure includes a gate structure for a fin field effect transistor. 
     
     
         6 . A semiconductor device having improved performance, comprising:
 a gate structure formed on a substrate, the gate structures being formed in an operative relationship with active areas formed in the substrate;   dummy structures formed at a periphery of an array of gate structures;   a stress liner formed on the gate structure and dummy structures, the stress liner including stress relieved vertical surfaces wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect during ion implantation maintain as-deposited stresses.   
     
     
         7 . The device as recited in  claim 6 , wherein the gate structures include gate structures for N-type field effect transistors. 
     
     
         8 . The device as recited in  claim 6 , further comprising a P-type field effect transistor having a transverse compressive stress relieved stress liner on associated gate structures. 
     
     
         9 . The device as recited in  claim 6 , wherein the gate structure includes a gate structure for a fin field effect transistor.