Local interconnect having increased misalignment tolerance

Abstract

A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

1 . A method for forming an interconnect in a semiconductor memory device, comprising:
 forming a pair of source select transistors on a substrate;   forming a source region in the substrate between the pair of source select transistors;   forming a first inter-layer dielectric between the pair of source select transistors;   depositing a mask layer over the pair of source select transistors and the first inter-layer dielectric,   wherein the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors;   etching the semiconductor memory device to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region; and   forming a metal contact in the local interconnect area.   
     
     
         2 . The method of  claim 1 , wherein the width of the local interconnect area is between 40 and 60 nm less than a distance between the pair of source select cells. 
     
     
         3 . The method of  claim 1  wherein forming each of the pair of source select transistors comprises:
 forming a first dielectric layer on the substrate, 
 forming a charge storage layer on the first dielectric layer, 
 forming a second dielectric layer on the charge storage layer, and 
 forming a control gate layer on the second dielectric layer. 
 
     
     
         4 . The method of  claim 3 , wherein the control gate layer is a polysilicon layer having a thickness ranging from about 1000 Å to about 2000 Å. 
     
     
         5 . The method of  claim 3 , wherein the charge storage layer is a silicon nitride layer having a thickness ranging from about 25 Å to about 500 Å. 
     
     
         6 . The method of  claim 5 , wherein the silicon nitride layer is configured to store more than one bit of information therein. 
     
     
         7 . The method of  claim 3 , further comprising: forming a gate silicide region in the control gate layer of each source select transistors. 
     
     
         8 . The method of  claim 1 , further comprising: forming a source silicide region in the source region. 
     
     
         9 . The method of  claim 1 , further comprising, prior to forming the first inter-layer dielectric:
 forming a dielectric liner layer over the substrate and the pair of source select transistors; and   forming a spacer layer over the dielectric liner layer,   wherein the spacer layer is etched to expose at least a portion of the dielectric liner layer over the source region.   
     
     
         10 . The method of  claim 9 , further comprising forming a dielectric etch stop layer over the spacer layer and the dielectric liner layer prior to forming the first inter-layer dielectric. 
     
     
         11 . The method of  claim 10 , wherein the dielectric etch stop layer is a silicon nitride layer having a thickness ranging from about 100 Å to about 1000 Å. 
     
     
         12 . The method of  claim 10 , further comprising polishing the first inter-layer dielectric to expose an upper surface of the dielectric etch stop layer. 
     
     
         13 . The method of  claim 12 , wherein polishing the first inter-layer dielectric is performed by subjecting the semiconductor device to a selective slurry. 
     
     
         14 . The method of  claim 10 , wherein etching the semiconductor memory device to remove a portion of the first inter-layer dielectric in the local interconnect area, further comprises:
 etching the first inter-layer dielectric within the local interconnect area using a first etch chemistry; and   etching the dielectric stop layer and dielectric liner layer using a second etch chemistry.   
     
     
         15 . The method of  claim 1 , further comprising forming a barrier metal layer in the local interconnect area prior to forming the metal contact. 
     
     
         16 . The method of  claim 15 , wherein
 the barrier metal layer is one of titanium layer followed by a titanium nitride layer, each layer having a thickness ranging from about 50 Å to about 300 Å; and   the metal contact comprises tungsten,   wherein the metal contact is polished to form a tungsten strap.   
     
     
         17 . A semiconductor device, comprising:
 a substrate having a source region formed in an active region;   a pair of source select transistors formed above the substrate on opposite sides of the source region;   a first inter-layer dielectric formed above the substrate in between the pair of source select transistors; and   a local interconnect comprising a metal formed adjacent the first inter-layer dielectric,   wherein the local interconnect has a width narrower than a distance between the pair of source select transistors.   
     
     
         18 . The semiconductor device of  claim 17 , wherein each side of the local interconnect is separated from a dielectric formed adjacent a sidewall of a respective one of the pair of source select transistors by between 20 and 30 nm. 
     
     
         19 . The semiconductor device of  claim 17 ,
 wherein the source region includes a source silicide region formed on at least a portion of an upper surface thereof, and   wherein the local interconnect has a width at least as wide as the source silicide region.   
     
     
         20 . A method of fabricating a semiconductor device having a pair of select transistors formed over a substrate, comprising:
 forming a source region between the pair of select transistors, the source region have a silicide region formed in an upper surface thereof;   forming a liner oxide layer over the pair of select transistors and the source region;   forming spacers adjacent the interior sidewalls of the pair of select transistors over the liner oxide layer;   depositing a inter-layer dielectric between the spacers;   etching the inter-layer dielectric and the liner oxide layer to form an interconnect area have a width less than a distance between the pair of select transistors; and   forming a metal contact within the interconnect area.