Semiconductor Devices Including a Layer of Polycrystalline Silicon Having a Smooth Morphology

Abstract

A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are provided. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.

1 - 14 . (canceled) 
     
     
         15 . A semiconductor device precursor comprising:
 a semiconductor substrate;   silicon dioxide formed on said semiconductor substrate, the surface of said silicon dioxide having been doped with hydrogen ions deposited by a plasma source ion implantation process, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with silicon dioxide doped with ions deposited by a Kauffman ion implantation process; and   polycrystalline silicon formed on said silicon dioxide, said polycrystalline silicon having a smooth morphology.   
     
     
         16 . The semiconductor device precursor of  claim 15  wherein the semiconductor substrate comprises at least one of gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass, and quartz. 
     
     
         17 . A field effect transistor comprising:
 a semiconductor substrate;   silicon dioxide formed on at least a portion of said semiconductor substrate, the surface of said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with silicon dioxide doped with ions deposited by a Kauffman ion implantation process;   polycrystalline silicon formed on at least a portion of said silicon dioxide, said polycrystalline silicon having a smooth morphology;   a gate oxide formed on said semiconductor substrate from said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation; and   a source and a drain formed in said semiconductor substrate with a gate electrode formed on said semiconductor substrate from said polycrystalline silicon to form a field effect transistor.   
     
     
         18 . The transistor of  claim 17  wherein the semiconductor substrate comprises at least one of gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass, and quartz. 
     
     
         19 . A memory array comprising:
 a semiconductor substrate;   silicon dioxide formed on at least a portion of said semiconductor substrate, wherein hydrogen ions are implanted into at least a portion of the surface of said silicon dioxide by plasma source ion implantation, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with a silicon dioxide doped with ions deposited by a Kauffman ion implantation process;   polycrystalline silicon formed over at least said portion of said silicon dioxide into which said hydrogen ions were implanted, said polycrystalline silicon having a smooth morphology;   a plurality of memory cells arranged in rows and columns, each of said plurality of memory cells comprising at least one field effect transistor;   a gate oxide for each of said field effect transistors formed on said semiconductor substrate from said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation;   a source and a drain for each of said field effect transistors formed in said semiconductor substrate; and   a gate electrode for each of said field effect transistors formed on said semiconductor substrate from said polycrystalline silicon.   
     
     
         20 . The memory array of  claim 19  wherein the semiconductor substrate comprises at least one of gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass, and quartz. 
     
     
         21 . The memory array of  claim 19  comprising DRAM. 
     
     
         22 . The memory array of  claim 19  comprising SRAM. 
     
     
         23 . A semiconductor wafer comprising:
 a wafer including a semiconductor substrate, said wafer being divided into a plurality of die;   silicon dioxide formed on at least a portion of said semiconductor substrate, on each of said plurality of die hydrogen ions are implanted into at least a portion of the surface of said silicon dioxide by plasma source ion implantation, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with a silicon dioxide doped with ions deposited by a Kauffman ion implantation process;   polycrystalline silicon formed over at least said portion of said silicon dioxide into which said hydrogen ions were implanted, said polycrystalline silicon having a smooth morphology;   a repeating series of gate oxides formed on said semiconductor substrate from said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation;   a repeating series of sources and drains for at least one field effect transistor formed on each of said plurality of die, said series of sources and drains being formed on said semiconductor substrate; and   a repeating series of gate electrodes for at least one field effect transistor formed on each of said plurality of die, said series of gate electrodes being formed on said semiconductor substrate from said polycrystalline silicon.   
     
     
         24 . A thin film transistor comprising:
 a semiconductor substrate formed from a material selected from the group consisting of silicon dioxide, quartz and glass, the surface of said semiconductor substrate having hydrogen ions implanted therein by plasma source ion implantation, wherein said semiconductor substrate has reduced sputtered metal contaminants in comparison with a semiconductor substrate doped with ions deposited by a Kauffman ion implantation process;   polycrystalline silicon formed on at least a portion of said semiconductor substrate, said polycrystalline silicon having a smooth morphology;   insulating material formed on at least a portion of said polycrystalline silicon;   a gate oxide formed from said insulating material;   a source region and a drain region formed in said polycrystalline silicon; and   a gate electrode formed on said insulating material.