Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a semiconductor layer, a gate trench formed in the semiconductor layer, a source region exposed at a front surface of the semiconductor layer and forming a curved portion of the gate trench, a channel region forming a planar portion of the gate trench, a drain region forming a bottom surface of the gate trench, a gate oxide film formed on an inner surface of the gate trench, a gate electrode embedded inside the gate trench in the planar portion, an embedding insulator film embedded inside the gate trench in the curved portion, a contact trench formed in the semiconductor layer in self-alignment with the curved portion of the gate trench, and a channel contact region formed on a bottom surface of the contact trench.

1 . A semiconductor device, comprising:
 a semiconductor layer having a front surface and a rear surface;   a gate trench formed in the semiconductor layer, the gate trench including an open end, a curved portion formed at the open end to have an opening width growing larger like a trumpet toward the front surface of the semiconductor layer and a planar portion formed closer to the rear surface of the semiconductor layer with respect to the curved portion to have a constant opening width;   a first-conductivity-type source region exposed at the front surface of the semiconductor layer and configured to form the curved portion of the gate trench;   a second-conductivity-type channel region formed closer to the rear surface of the semiconductor layer with respect to the source region to adjoin to the source region and configured to form the planar portion of the gate trench;   a first-conductivity-type drain region formed closer to the rear surface of the semiconductor layer with respect to the channel region to adjoin to the channel region and configured to form a bottom surface of the gate trench;   a gate oxide film formed on an inner surface of the gate trench;   a gate electrode embedded inside the gate trench in the planar portion of the gate trench;   an embedding insulator film embedded inside the gate trench in the curved portion of the gate trench;   a contact trench formed in the semiconductor layer in self-alignment with the curved portion of the gate trench, the contact trench extending through the source region and having a deepest portion reaching the channel region; and   a second-conductivity-type channel contact region formed on a bottom surface of the contact trench.   
     
     
         2 . The device of  claim 1 , wherein the portion of the gate oxide film formed in the curved portion is two to four times as thick as the portion of the gate oxide film formed in the planar portion. 
     
     
         3 . The device of  claim 1 , wherein the alignment error of the contact trench with respect to the gate trench is 0.1 μm or less. 
     
     
         4 . The device of  claim 1 , wherein the contact trench has an opening width of from 0.2 μm to 0.5 μm. 
     
     
         5 . The device of  claim 1 , wherein the semiconductor layer is formed of a silicon semiconductor layer. 
     
     
         6 . A semiconductor device manufacturing method, comprising:
 providing a semiconductor layer having a front surface and a rear surface;   forming a hard mask on the front surface of the semiconductor layer, the semiconductor layer including a first-conductivity-type source region exposed at the front surface of the semiconductor layer, a second-conductivity-type channel region formed closer to the rear surface of the semiconductor layer with respect to the source region to adjoin to the source region and a first-conductivity-type drain region formed closer to the rear surface of the semiconductor layer with respect to the channel region to adjoin to the channel region;   forming a gate trench by etching the semiconductor layer using the hard mask, the gate trench extending through the source region and the channel region and having a deepest portion reaching the drain region;   forming a gate oxide film on an inner surface of the gate trench;   forming a gate electrode so as to expose a portion of the gate oxide film by embedding an electrode material inside the gate trench to reach at least an upper end of the channel region in a thickness direction of the gate trench;   forming a curved portion at an open end of the gate trench to have an opening width growing larger like a trumpet toward the front surface of the semiconductor layer and simultaneously forming a planar portion closer to the rear surface of the semiconductor layer with respect to the curved portion to have a constant opening width by subjecting the semiconductor layer to thermal oxidation and oxidizing the exposed portion of the gate oxide film in a state where the front surface of the semiconductor layer is covered with the hard mask;   forming an embedding insulator film in the curved portion of the gate trench by embedding an insulating material inside the gate trench;   forming a contact trench in the semiconductor layer in self-alignment with the curved portion of the gate trench by etching the semiconductor layer using the embedding insulator film as a mask, the contact trench extending through the source region and having a deepest portion reaching the channel region; and   forming a channel contact region in the channel region by injecting second-conductivity-type ions into a bottom surface of the contact trench.   
     
     
         7 . The method of  claim 6 , wherein forming the gate electrode comprises:
 depositing the electrode material to fill the gate trench with the electrode material; and   exposing a portion of the gate oxide film by etching and leveling down an upper surface of the deposited electrode material.   
     
     
         8 . The method of  claim 6 , wherein forming the embedding insulator film comprises:
 depositing the insulating material until at least the front surface of the semiconductor layer is concealed; and   etching back the deposited insulating material until the front surface of the semiconductor layer is exposed.   
     
     
         9 . The method of  claim 6 , wherein forming the hard mask comprises forming a two-layer film composed of a SiO 2  film and a SiN film by first forming the SiO 2  film and then forming the SiN film on the SiO 2  film.