Thin film transistor and method of manufacturing the same

Abstract

A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.

1 . A thin film transistor (“TFT”) comprising:
 a gate electrode; 
 a semiconductor layer overlapping with the gate electrode; 
 a gate insulating layer disposed between the gate electrode and the semiconductor layer; 
 a source electrode overlapping with the semiconductor layer; 
 a drain electrode overlapping with the semiconductor layer and spaced apart from the source electrode; and 
 a graphene pattern disposed between the semiconductor layer and at least one of the source electrode and the drain electrode. 
 
     
     
         2 . The TFT of  claim 1 , wherein the semiconductor layer is disposed on the gate electrode,
 the graphene pattern is disposed on the semiconductor layer, and   the source electrode and the drain electrode are disposed on the graphene pattern.   
     
     
         3 . The TFT of  claim 2 , further comprising:
 a passivation layer disposed on the source electrode and the drain electrode; and   a second graphene pattern disposed between the source electrode and the passivation layer and disposed between the drain electrode and the passivation layer.   
     
     
         4 . The TFT of  claim 3 , wherein the passivation layer comprises silicon oxide. 
     
     
         5 . The TFT of  claim 4 , wherein the passivation layer comprises a first layer making contact with the second graphene pattern and a second layer disposed on the first layer,
 the first layer comprises the silicon oxide, and   the second layer comprises silicon nitride.   
     
     
         6 . The TFT of  claim 3 , wherein the second graphene pattern covers upper and side surfaces of each of the source and drain electrodes. 
     
     
         7 . The TFT of  claim 1 , wherein the semiconductor layer comprises an oxide semiconductor. 
     
     
         8 . The TFT of  claim 7 , further comprising an etch stopper disposed between the semiconductor layer and the graphene pattern and overlapping with a portion of the semiconductor layer formed in an area between the source electrode and the drain electrode. 
     
     
         9 . The TFT of  claim 1 , wherein the drain electrode is disposed on the source electrode. 
     
     
         10 . The TFT of  claim 9 , wherein a first portion of the graphene pattern is disposed between the drain electrode and the semiconductor layer, and
 a second portion of the graphene pattern is disposed between the drain electrode and the gate insulating layer.   
     
     
         11 . The TFT of  claim 9 , further comprising:
 an insulating layer disposed between the source electrode and the drain electrode;   a second graphene pattern disposed between the source electrode and the insulating layer; and   a third graphene pattern disposed between the drain electrode and the insulating layer.   
     
     
         12 . The TFT of  claim 1 , wherein at least one of the source electrode and the drain electrode comprises a plurality of electrode layers. 
     
     
         13 . The TFT of  claim 12 , wherein at least one of the source electrode and the drain electrode comprises a first electrode layer making contact with the graphene pattern and a second electrode layer making contact with the first electrode layer,
 the first electrode layer comprises one of titanium (Ti), molybdenum (Mo) and an alloy thereof, and   the second electrode layer comprises copper (Cu).   
     
     
         14 . A method of manufacturing a TFT, the method comprising:
 forming a gate electrode on a base substrate;   forming a gate insulating layer on the gate electrode;   forming a semiconductor layer overlapping with the gate electrode on the gate insulating layer;   forming a graphene layer on the semiconductor layer;   forming a source electrode and a drain electrode on the graphene layer; and   patterning the graphene layer between the source and drain electrodes to form a graphene pattern.   
     
     
         15 . The method of  claim 14 , wherein forming the graphene layer comprises growing graphene on the semiconductor layer. 
     
     
         16 . The method of  claim 14 , wherein forming the graphene layer comprises transferring graphene to the semiconductor layer. 
     
     
         17 . The method of  claim 14 , wherein patterning the graphene layer comprises ashing the graphene layer using an oxygen plasma. 
     
     
         18 . The method of  claim 14 , further comprising:
 forming a second graphene pattern on the source electrode and the drain electrode; and   forming a passivation layer on the second graphene pattern.   
     
     
         19 . The method of  claim 18 , wherein forming the source electrode, the drain electrode and the second graphene pattern comprises:
 forming a source-drain electrode layer on the graphene layer;   forming a second graphene layer on the source-drain electrode layer;   patterning the second graphene layer; and   patterning the source-drain electrode layer.   
     
     
         20 . The method of  claim 19 , wherein forming the second graphene layer comprises growing graphene on the source-drain electrode layer. 
     
     
         21 . The method of  claim 19 , wherein forming the second graphene layer comprises transferring the graphene to the source-drain electrode layer. 
     
     
         22 . The method of  claim 18 , wherein forming the source electrode, the drain electrode and the second graphene pattern comprises:
 forming a source-drain electrode layer on the graphene layer;   patterning the source-drain electrode layer; and   selectively growing a graphene on the source-drain electrode layer.   
     
     
         23 . The method of  claim 18 , wherein the passivation layer comprises silicon oxide. 
     
     
         24 . The method of  claim 23 , wherein the passivation layer comprises a first layer making contact with the second graphene pattern and a second layer disposed on the first layer,
 the first layer comprises the silicon oxide, and   the second layer comprises silicon nitride.   
     
     
         25 . The method of  claim 14 , wherein the semiconductor layer comprises an oxide semiconductor. 
     
     
         26 . The method of  claim 25 , further comprising forming an etch stopper disposed between the semiconductor layer and the graphene pattern and overlapping with a portion of the semiconductor layer formed in an area between the source electrode and the drain electrode. 
     
     
         27 . The method of  claim 14 , wherein at least one of the source electrode and the drain electrode comprises a plurality of electrode layers. 
     
     
         28 . The method of  claim 27 , wherein at least one of the source electrode and the drain electrode comprises a first electrode layer making contact with the graphene pattern and a second electrode layer making contact with the first electrode layer,
 the first electrode layer comprises one of titanium (Ti), molybdenum (Mo) and an alloy thereof, and   the second electrode layer comprises copper (Cu).   
     
     
         29 . A method of manufacturing a TFT, the method comprising:
 forming a source electrode on a base substrate;   forming an insulating layer on the source electrode;   forming a drain electrode on the insulating layer;   forming a graphene pattern on the drain electrode;   forming a semiconductor layer on the graphene pattern;   patterning the semiconductor layer;   forming a gate insulating layer on the semiconductor layer; and   forming a gate electrode on the gate insulating layer.   
     
     
         30 . The method of  claim 29 , wherein a first portion of the graphene pattern is disposed between the drain electrode and the semiconductor layer, and
 a second portion of the graphene pattern is disposed between the drain electrode and the gate insulating layer.   
     
     
         31 . The method of  claim 29 , further comprising:
 forming a second graphene pattern between the source electrode and the insulating layer; and   forming a third graphene pattern between the drain electrode and the insulating layer.