Semiconductor apparatus and stacked semiconductor apparatus

Abstract

A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

1 . A semiconductor apparatus comprising:
 a TSV formed to be electrically connected with another chip; and   a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.   
     
     
         2 . The semiconductor apparatus according to  claim 1 , wherein the TSV test unit comprises:
 a charge node electrically connected with the TSV and having capacitance of the capacitance component of the TSV;   a charge node supply section configured to charge the charge node in response to a test pulse with a predetermined pulse width; and   a test result checking section configured to generate the TSV abnormality signal depending upon a voltage level of the charge node.   
     
     
         3 . The semiconductor apparatus according to  claim 2 , wherein the test result checking section comprises:
 a determination node sink stage configured to discharge a determination node depending upon the voltage level of the charge node; and   a signal output stage configured to output the TSV abnormality signal in reference to a voltage level of the determination node.   
     
     
         4 . The semiconductor apparatus according to  claim 3 , wherein the signal output stage comprises:
 a latch circuit electrically connected with the determination node.   
     
     
         5 . The semiconductor apparatus according to  claim 3 , wherein the test result checking section further comprises:
 a determination node initialization stage configured to initialize the voltage level of the determination node in response to a reset signal.   
     
     
         6 . The semiconductor apparatus according to  claim 2 , wherein the TSV test unit further comprises:
 a charge node initializing section configured to initialize the voltage level of the charge node in response to a reset signal.   
     
     
         7 . The semiconductor apparatus according to  claim 1 , further comprising:
 an output unit configured to receive and latch a plurality of TSV abnormality signals outputted from a plurality of TSV test units allocated to a plurality of TSVs, and serially output the plurality of TSV abnormality signals in response to a clock signal.   
     
     
         8 . The semiconductor apparatus according to  claim 7 , wherein the output unit comprises:
 a plurality of flip-flops connected in series and configured to respectively receive the plurality of TSV abnormality signals.   
     
     
         9 . The semiconductor apparatus according to  claim 7 , further comprising:
 a pad configured to output an output signal of the output unit to an outside.   
     
     
         10 . A stacked semiconductor apparatus comprising:
 a first chip having a first TSV connected between a first node and a second node;   a second chip having a second TSV connected between a third node and a fourth node; and   a connection unit configured to electrically connect the second node and the third node with each other,   wherein the first chip includes a first TSV test unit configured to check a capacitance value of the first TSV and generate a first single test result in a single TSV test mode, and supply a power supply voltage to the first node in a stacked TSV test mode, and   wherein the second chip includes a second TSV test unit configured to check a capacitance value of the second TSV and generate a second single test result in the single TSV test mode, and electrically connect the third node and a fifth node with each other in the stacked TSV test mode.   
     
     
         11 . The stacked semiconductor apparatus according to  claim 10 , wherein the first TSV test unit comprises:
 a first node supply section configured to supply the power supply voltage to the first node in response to a single test pulse signal in the single TSV test mode, and supply the power supply voltage to the first node in the stacked TSV test mode; and   a first single test result checking section configured to generate the first single test result depending upon a voltage level of the first node.   
     
     
         12 . The stacked semiconductor apparatus according to  claim 11 , wherein the first TSV test unit further comprises:
 a first node sink section configured to initialize the voltage level of the first node in response to a first node control signal in the single TSV test mode.   
     
     
         13 . The stacked semiconductor apparatus according to  claim 11 ,
 wherein the single test pulse signal is a signal activated with a predetermined pulse width, and   wherein, in the single TSV test mode, the first node is charged by the first node supply section for the predetermined pulse width.   
     
     
         14 . The stacked semiconductor apparatus according to  claim 13 , wherein the first single test result checking section generates as the first single test result whether a voltage of the first node is equal to or larger than a predetermined level. 
     
     
         15 . The stacked semiconductor apparatus according to  claim 14 , wherein the first single test result checking section comprises:
 a latch stage connected with a determination node and configured to latch a voltage level of the determination node; and   a determination node sink stage configured to discharge the determination node depending upon the voltage level of the first node,   wherein the first single test result is generated depending upon a latched value of the latch stage.   
     
     
         16 . The stacked semiconductor apparatus according to  claim 15 , wherein, when the voltage of the first node is equal to or larger than the predetermined level, the determination node is sufficiently discharged to change the latched value of the latch stage. 
     
     
         17 . The stacked semiconductor apparatus according to  claim 16 , wherein the first single test result checking section further comprises:
 a determination node supply stage configured to initialize the voltage of the determination node in response to a determination node reset signal.   
     
     
         18 . The stacked semiconductor apparatus according to  claim 11 , wherein the first node supply section comprises:
 a first switch stage configured to electrically connect the power supply voltage and the first node with each other in response to a first switch control signal; and   a first select stage configured to select one of the single test pulse signal and a stack test signal as the first switch control signal in response to a mode select signal,   wherein the mode select signal is a signal with different values in the single TSV test mode and the stacked TSV test mode, and   wherein the stack test signal is a signal which is activated in the stacked TSV test mode.   
     
     
         19 . The stacked semiconductor apparatus according to  claim 10 , wherein the second TSV test unit comprises:
 a third node supply section configured to supply the power supply voltage to the third node in response to a single test pulse signal in the single TSV test mode;   a third node connecting section configured to electrically connect the third node and the fifth node with each other in the stacked TSV test mode; and   a second single test result checking section configured to generate the second single test result depending upon a voltage level of the third node.   
     
     
         20 . The stacked semiconductor apparatus according to  claim 19 , wherein the third node connecting section initializes the voltage level of the third node in the single TSV test mode. 
     
     
         21 . The stacked semiconductor apparatus according to  claim 20 , wherein the third node connecting section comprises:
 a second switch stage configured to electrically connect the third node and a sixth node with each other in response to a third node control signal; and   a second select stage configured to electrically connect one of the fifth node and a ground voltage with the sixth node in response to a mode select signal,   wherein the mode select signal has different values in the single TSV test mode and the stacked TSV test mode.   
     
     
         22 . The stacked semiconductor apparatus according to  claim 19 , wherein the fifth node is electrically connected with a pad for communicating with an external device. 
     
     
         23 . The stacked semiconductor apparatus according to  claim 19 ,
 wherein the single test pulse signal is a signal activated with a predetermined pulse width, and   wherein, in the single TSV test mode, the third node is charged by the third node supply section for the predetermined pulse width.   
     
     
         24 . The stacked semiconductor apparatus according to  claim 23 , wherein the second single test result checking section indicates with the second single test result whether a voltage of the third node is equal to or larger than a predetermined level. 
     
     
         25 . The stacked semiconductor apparatus according to  claim 24 , wherein the second single test result checking section comprises:
 a latch stage connected with a determination node and configured to latch a voltage level of the determination node; and   a determination node sink stage configured to discharging the determination node depending upon the voltage level of the third node,   wherein the second single test result is generated depending upon a latched value of the latch stage.   
     
     
         26 . The stacked semiconductor apparatus according to  claim 24 , wherein, when the voltage of the third node is equal to or larger than the predetermined level, a degree to which the determination node sink stage discharges the determination node is sufficiently large to change the latched value of the latch stage. 
     
     
         27 . The stacked semiconductor apparatus according to claim  26 , wherein the second single test result checking section further comprises:
 a determination node supply stage configured to initialize the voltage of the determination node in response to a determination node reset signal.   
     
     
         28 . The stacked semiconductor apparatus according to  claim 11 ,
 wherein the first chip and the second chip are manufactured through same manufacturing processes, and   wherein the first TSV test unit further comprises:   a first node sink section configured to initialize the voltage level of the first node in response to a first node control signal in the single TSV test mode, wherein the first node sink section comprises:   a third switch stage configured to electrically connect the first node and an eighth node with each other in response to the first node control signal; and   a third select stage configured to electrically connect one of a seventh node and the ground voltage with the eighth node in response to a mode select signal.   
     
     
         29 . The stacked semiconductor apparatus according to  claim 28 , wherein the first node control signal is inputted to maintain a deactivated state in the stacked TSV test mode. 
     
     
         30 . The stacked semiconductor apparatus according to  claim 28 , wherein the seventh node is electrically connected with a pad for communicating with an external device. 
     
     
         31 . The stacked semiconductor apparatus according to  claim 19 ,
 wherein the first chip and the second chip are manufactured through the same manufacturing processes, and   wherein the third node supply section comprises:   a fourth switch stage configured to electrically connect the power supply voltage and the third node with each other in response to a fourth switch control signal; and   a fourth select stage configured to select one of the single test pulse signal and a stack test signal in response to a mode select signal and output the fourth switch control signal,   wherein the mode select signal is a signal that has different values in the single TSV test mode and the stacked TSV test mode, and   wherein the stack test signal is a signal that is deactivated in the stacked TSV test mode.   
     
     
         32 . The stacked semiconductor apparatus according to  claim 19 ,
 wherein the second chip further comprises:   a current sensing circuit configured to check amount of current through the fifth node, and   wherein the current sensing circuit generates a stack test result depending upon the amount of current.   
     
     
         33 . The stacked semiconductor apparatus according to  claim 21 , wherein the second chip comprises:
 a plurality of TSVs including the second TSV; and   a plurality of TSV test units each allocated to at least two of the plurality of TSVs and configured in the same manner as the second TSV test unit.   
     
     
         34 . The stacked semiconductor apparatus according to  claim 33 , wherein the second chip further comprises:
 a third node control signal generation unit configured to receive a test input signal serially inputted in response to a clock signal, generate a plurality of third node control signals, and provide the plurality of third node control signals to the plurality of TSV test units.   
     
     
         35 . The stacked semiconductor apparatus according to  claim 34 ,
 wherein the third node control signal generation unit includes a plurality of flip-flops,   wherein the plurality of flip-flops are configured to receive and latch the test input signal in synchronization with the clock signal, and   wherein latched values of the plurality of flip-flops are provided to the plurality of TSV test units as the third node control signals.   
     
     
         36 . The stacked semiconductor apparatus according to  claim 10 , wherein the first chip comprises:
 a plurality of TSVs including the first TSV; and   a plurality of TSV test units each allocated to at least two of the plurality of TSVs and configured in the same manner as the first TSV test unit.   
     
     
         37 . The stacked semiconductor apparatus according to  claim 36 , wherein the first chip further comprises:
 an output unit configured to receive and latch a plurality of single test results including the first single test result outputted by the plurality of TSV test units, and serially output the plurality of single test results in response to a clock signal.   
     
     
         38 . The stacked semiconductor apparatus according to  claim 37 , wherein the output unit comprises:
 a plurality of flip-flops connected in series and configured to respectively receive the plurality of single test results.   
     
     
         39 . The stacked semiconductor apparatus according to  claim 37 , wherein the first chip further comprises:
 a pad configured to output an output signal of the output unit to an external device.   
     
     
         40 . The stacked semiconductor apparatus according to  claim 10 , wherein the second chip comprises:
 a plurality of TSVs including the second TSV; and   a plurality of TSV test units each allocated to at least two of the plurality of TSVs and configured in the same manner as the second TSV test unit.   
     
     
         41 . The stacked semiconductor apparatus according to  claim 40 , wherein the second chip further comprises:
 an output unit configured to receive and latch a plurality of single test results including the second single test results outputted from the plurality of TSV test units, and serially output the plurality of single test results in response to a clock signal.   
     
     
         42 . The stacked semiconductor apparatus according to  claim 41 , wherein the output unit comprises:
 a plurality of flip-flops connected in series and configured to respectively receive the plurality of single test results.   
     
     
         43 . The stacked semiconductor apparatus according to  claim 41 , wherein the second chip further comprises:
 a pad configured to output an output signal of the output unit to an external device.