Semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes: a semiconductor substrate including an active region defined by an isolation layer; a gate line defining a bit line contact region in the active region and extending in one direction; a dielectric layer covering the semiconductor substrate and the gate line formed in the semiconductor substrate; a bit line contact hole formed in the dielectric layer and exposing the bit line contact region; and a bit line contact spaced apart from a sidewall of the bit line contact hole and formed in the bit line contact hole.

1 . A semiconductor device comprising:
 a semiconductor substrate including an active region defined by an isolation layer;   a gate line defining a bit line contact region in the active region and extending in one direction;   a dielectric layer covering the semiconductor substrate and the gate line formed in the semiconductor substrate;   a bit line contact hole formed in the dielectric layer and exposing the bit line contact region; and   a bit line contact spaced apart from a sidewall of the bit line contact hole and formed in the bit line contact hole.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a bit line coupled to the bit line contact and extending in a direction crossing the gate line. 
     
     
         3 . The semiconductor device of  claim 2 , further comprising a liner layer covering the bit line, the dielectric layer, and exposed regions of the bit line contact hole above the semiconductor substrate. 
     
     
         4 . A method for fabricating a semiconductor device, comprising:
 providing a semiconductor substrate including an active region defined by an isolation layer;   forming a gate line defining a bit line contact region in the active region and extending in one direction;   forming a dielectric layer over the semiconductor substrate and the gate line formed in the semiconductor substrate;   forming a bit line contact hole formed in the dielectric layer and exposing the bit line contact region;   forming a spacer on a sidewall of the bit line contact hole; and   forming a bit line contact to fill the bit line contact hole including the spacer formed in the bit line contract hole.   
     
     
         5 . The method of  claim 4 , further comprising:
 forming a bit line structure coupled to the bit line contact and extending in a direction crossing the gate line; and   removing the spacer formed on the sidewalls of the bit line contact hole.   
     
     
         6 . The method of  claim 5 , further comprising:
 forming a liner layer covering the bit line, the dielectric layer, and exposed regions of the bit line contact hole above the semiconductor substrate.   
     
     
         7 . The method of  claim 5 , wherein the removing of the spacer formed on the sidewalls of the bit line contact hole is performed by a blanket etch process using an etching selectivity between the spacer and the dielectric layer. 
     
     
         8 . The method of  claim 4 , wherein the forming of a gate line defining a bit line contact region in the active region and extending in one direction comprises:
 forming a first hard mask pattern formed over the semiconductor substrate to expose a region where the gate line is to be formed;   forming a gate-line trench by etching the active region using the first hard mask pattern as an etch mask;   removing the first hard mask pattern; and   forming the gate line to at least partially fill the gate-line trench.   
     
     
         9 . The method of  claim 8 , wherein the forming of a gate line defining a bit line contact region in the active region and extending in one direction further comprises:
 forming a gate dielectric layer over the surface of the gate-line trench after the first hard mask pattern is removed.   
     
     
         10 . The method of  claim 8 , wherein the first hard mask pattern includes an amorphous carbon layer (ALC), silicon oxynitride (SiON), and bottom anti-reflective coating (BARC). 
     
     
         11 . The method of  claim 8 , wherein the forming of the gate line to at least partially fill the gate-line trench comprises:
 forming a gate conductive layer to fill the gate-line trench;   performing a planarization process until the upper surface of the active region is exposed; and   etching the gate conductive layer to form the buried-type gate line.   
     
     
         12 . The method of  claim 4 , wherein the gate line includes titanium nitride (TIN), tungsten (W), and a combination thereof. 
     
     
         13 . The method of  claim 4 , wherein the forming of a dielectric layer over the semiconductor substrate and the gate line formed in the semiconductor substrate comprises:
 forming a first dielectric layer over a resultant structure including the gate line and the semiconductor substrate to cover the upper portion of the gate line; and   forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer is used to form the spacer.   
     
     
         14 . The method of  claim 13 , wherein the first dielectric layer is formed of a material having an etching selectivity with the second dielectric layer. 
     
     
         15 . The method of  claim 13 , wherein the first dielectric layer comprises silicon nitride, and the second dielectric layer comprises an oxide-based material. 
     
     
         16 . The method of  claim 4 , wherein the forming of a spacer on a sidewall of the bit line contact hole comprises:
 forming a spacer dielectric layer over a resultant structure including the bit line contact hole and the second dielectric layer; and   performing a blanket etch process on the spacer dielectric layer so that the spacer dielectric layer remains only on the sidewalls of the bit line contact hole.   
     
     
         17 . The method of  claim 16 , wherein the spacer dielectric layer is formed by conformally depositing an oxide-based material.