US2012306729A1PendingUtilityA1
El display panel, power supply line drive apparatus, and electronic device
Est. expiryJun 30, 2027(~0.9 yrs left)· nominal 20-yr term from priority
G09G 2330/02G09G 3/30G09G 2320/045G09G 2330/021G09G 3/3233G09G 2310/0256G09G 2300/0866G09G 2300/0426G09G 3/3275G09G 2300/0819G09G 2300/0842G09G 3/3266G09G 2310/0286G09G 2320/043G09G 2310/08H10K 59/131
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Claims
Abstract
Disclosed herein is an electroluminescence display panel including: a pixel circuit; a signal line; a scan line; a drive power supply line; a common power supply line; a power supply line drive circuit; a high-potential power supply line; and a low-potential power supply line.
Claims
exact text as granted — not AI-modified1 . A line drive apparatus, wherein in a layout pattern of the line drive apparatus:
a first drive line is connected to a first source/drain of a first transistor and a first source/drain of a second transistor, a first row of pixel circuits being connected to said first drive line; a second drive line is connected to a first source/drain of a third transistor and a first source/drain of a fourth transistor, a second row of pixel circuits being connected to said second drive line; a high-potential power supply line connects a second source/drain of the first transistor to a second source/drain of the third transistor, said high-potential power supply line not crossing said first drive line or said second drive line; a low-potential power supply line connects a second source/drain of the second transistor to a second source/drain of the fourth transistor.
2 . The line drive apparatus according to claim 1 , wherein in the layout pattern:
said low-potential power supply line crosses said first drive line and said second drive line.
3 . The line drive apparatus according to claim 1 , wherein in the layout pattern:
said high-potential power supply line crosses said first transistor, said second transistor, said third transistor, and fourth transistor.
4 . The line drive apparatus according to claim 1 , wherein in the layout pattern:
said low-potential power supply line crosses said first transistor, said second transistor, said third transistor, and fourth transistor.
5 . The line drive apparatus according to claim 1 , wherein in the layout pattern:
a first extraction wire connects said first source/drain of the second transistor to said first drive line.
6 . The line drive apparatus according to claim 5 , wherein in the layout pattern:
a second extraction wire connects said first source/drain of the fourth transistor to said second drive line.
7 . The line drive apparatus according to claim 6 , wherein in the layout pattern:
said low-potential power supply line crosses said first extraction wire and said second extraction wire.
8 . The line drive apparatus according to claim 6 , wherein in the layout pattern:
said high-potential power supply line crosses said first extraction wire and said second extraction wire.
9 . The line drive apparatus according to claim 1 , wherein in the layout pattern:
said low-potential power supply line overlaps said high-potential power supply line.
10 . The line drive apparatus according to claim 1 , wherein in the layout pattern:
a low power supply potential on said low-potential power supply line is lower than a high power supply potential on said high-potential power supply line.
11 . The line drive apparatus according to claim 1 , wherein in the layout pattern:
a first lead-out connects said second source/drain of the second transistor to said high-potential power supply line.
12 . The line drive apparatus according to claim 11 , wherein in the layout pattern:
a second lead-out connects said second source/drain of the fourth transistor to said high-potential power supply line.
13 . The line drive apparatus according to claim 12 , wherein in the layout pattern:
said low-potential power supply line crosses said first lead-out and said second lead-out.
14 . An electroluminescence display panel comprising the line drive apparatus according to claim 1 .
15 . The electroluminescence display panel according to claim 14 , further comprising:
a signal line connected to a pixel circuit in the first row of pixel circuits and to a pixel circuit in the second row of pixel circuits; a first scan line connected to said first row of pixel circuits, said first scan line being configured to provide a first write timing signal to said first row of pixel circuits; a second scan line connected to said second row of pixel circuits, said second scan line being configured to provide a second write timing signal to said second row of pixel circuits.
16 . An electronic device comprising the electroluminescence display panel according to claim 14 .
17 . An electronic device according to claim 16 , further comprising:
a system control block; and an operation input block for said system control block.Join the waitlist — get patent alerts
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